1. ECE 545
Lecture 9
Modeling of Circuits with a Regular Structure Aliases, Attributes, Functions, and Procedures

2. Required reading P. Chu, RTL Hardware Design using VHDL Chapters
14.5 For Generate Statement
14.6 Conditional Generate Statement
15.2 Data Types for Two-Dimensional Signals
15.3 Commonly Used Intermediate-Sized
RT-Level Components
Subprogram

3. Generate scheme for equations
ECE 448 – FPGA and ASIC Design with VHDL

4. Dataflow VHDL
Major instructions
Concurrent statements
concurrent signal assignment ()
conditional concurrent signal assignment
(when-else)
selected concurrent signal assignment
(with-select-when)
generate scheme for equations
(for-generate)

5. PARITY Example

6. PARITY: Block Diagram

7. PARITY: Entity Declaration
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY parity IS
PORT(
parity_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
parity_out : OUT STD_LOGIC );
END parity;

8. PARITY: Block Diagram xor_out(1) xor_out(2) xor_out(3) xor_out(4)

9. PARITY: Architecture ARCHITECTURE parity_dataflow OF parity IS
SIGNAL xor_out: std_logic_vector (6 downto 1);
BEGIN
xor_out(1) <= parity_in(0) XOR parity_in(1);
xor_out(2) <= xor_out(1) XOR parity_in(2);
xor_out(3) <= xor_out(2) XOR parity_in(3);
xor_out(4) <= xor_out(3) XOR parity_in(4);
xor_out(5) <= xor_out(4) XOR parity_in(5);
xor_out(6) <= xor_out(5) XOR parity_in(6);
parity_out <= xor_out(6) XOR parity_in(7);
END parity_dataflow;

10. PARITY: Architecture (2)
ARCHITECTURE parity_dataflow OF parity IS
SIGNAL xor_out: STD_LOGIC_VECTOR (6 DOWNTO 1);
BEGIN
xor_out(1) <= parity_in(0) XOR parity_in(1);
G2: FOR i IN 2 TO 6 GENERATE
xor_out(i) <= xor_out(i-1) XOR parity_in(i);
END GENERATE;
parity_out <= xor_out(6) XOR parity_in(7);
END parity_dataflow;

11. PARITY: Architecture (3)
ARCHITECTURE parity_dataflow OF parity IS
SIGNAL xor_out: STD_LOGIC_VECTOR (6 DOWNTO 1);
BEGIN
G2: FOR i IN 1 TO 7 GENERATE
left_xor: IF i=1 GENERATE
xor_out(i) <= parity_in(i-1) XOR parity_in(i);
END GENERATE;
middle_xor: IF (i >1) AND (i<7) GENERATE
xor_out(i) <= xor_out(i-1) XOR parity_in(i);
right_xor: IF i=7 GENERATE
parity_out <= xor_out(i-1) XOR parity_in(i);
END parity_dataflow;

12. PARITY: Block Diagram (2)
xor_out(0)
xor_out(1)
xor_out(2)
xor_out(3)
xor_out(4)
xor_out(5)
xor_out(6)
xor_out(7)

13. PARITY: Architecture ARCHITECTURE parity_dataflow OF parity IS
SIGNAL xor_out: STD_LOGIC_VECTOR (7 downto 0);
BEGIN
xor_out(0) <= parity_in(0);
xor_out(1) <= xor_out(0) XOR parity_in(1);
xor_out(2) <= xor_out(1) XOR parity_in(2);
xor_out(3) <= xor_out(2) XOR parity_in(3);
xor_out(4) <= xor_out(3) XOR parity_in(4);
xor_out(5) <= xor_out(4) XOR parity_in(5);
xor_out(6) <= xor_out(5) XOR parity_in(6);
xor_out(7) <= xor_out(6) XOR parity_in(7);
parity_out <= xor_out(7);
END parity_dataflow;

14. PARITY: Architecture (2)
ARCHITECTURE parity_dataflow OF parity IS
SIGNAL xor_out: STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
xor_out(0) <= parity_in(0);
G2: FOR i IN 1 TO 7 GENERATE
xor_out(i) <= xor_out(i-1) XOR parity_in(i);
END GENERATE G2;
parity_out <= xor_out(7);
END parity_dataflow;

15. For Generate Statement
label:
FOR identifier IN range GENERATE
{Concurrent Statements}
END GENERATE;

16. Conditional Generate Statement
If - Generate
label:
IF boolean_expression GENERATE
{Concurrent Statements}
END GENERATE;

17. Generate scheme for components
ECE 448 – FPGA and ASIC Design with VHDL

18. Structural VHDL
Major instructions
component instantiation (port map)
component instantiation with generic
(generic map, port map)
generate scheme for component instantiations
(for-generate)

19. Example 1

20. Example 1 w 8 11 s 1 3 4 7 12 15 2 f

21. A 4-to-1 Multiplexer LIBRARY ieee ; USE ieee.std_logic_1164.all ;
ENTITY mux4to1 IS
PORT ( w0, w1, w2, w3 : IN STD_LOGIC ;
s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
f : OUT STD_LOGIC ) ;
END mux4to1 ;
ARCHITECTURE Dataflow OF mux4to1 IS
BEGIN
WITH s SELECT
f <= w0 WHEN "00",
w1 WHEN "01",
w2 WHEN "10",
w3 WHEN OTHERS ;
END Dataflow ;

22. Straightforward code for Example 1
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY Example1 IS
PORT ( w : IN STD_LOGIC_VECTOR(0 TO 15) ;
s : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
f : OUT STD_LOGIC ) ;
END Example1 ;

23. Straightforward code for Example 1
ARCHITECTURE Structure OF Example1 IS
COMPONENT mux4to1
PORT ( w0, w1, w2, w3 : IN STD_LOGIC ;
s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
f : OUT STD_LOGIC ) ;
END COMPONENT ;
SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ;
BEGIN
Mux1: mux4to1 PORT MAP ( w(0), w(1), w(2), w(3), s(1 DOWNTO 0), m(0) ) ;
Mux2: mux4to1 PORT MAP ( w(4), w(5), w(6), w(7), s(1 DOWNTO 0), m(1) ) ;
Mux3: mux4to1 PORT MAP ( w(8), w(9), w(10), w(11), s(1 DOWNTO 0), m(2) ) ;
Mux4: mux4to1 PORT MAP ( w(12), w(13), w(14), w(15), s(1 DOWNTO 0), m(3) ) ;
Mux5: mux4to1 PORT MAP ( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f ) ;
END Structure ;

24. Modified code for Example 1
ARCHITECTURE Structure OF Example1 IS
COMPONENT mux4to1
PORT ( w0, w1, w2, w3 : IN STD_LOGIC ;
s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
f : OUT STD_LOGIC ) ;
END COMPONENT ;
SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ;
BEGIN
G1: FOR i IN 0 TO 3 GENERATE
Muxes: mux4to1 PORT MAP (
w(4*i), w(4*i+1), w(4*i+2), w(4*i+3), s(1 DOWNTO 0), m(i) ) ;
END GENERATE ;
Mux5: mux4to1 PORT MAP ( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f ) ;
END Structure ;

25. Example 2

26. Example 2 w w y y w w y y y y En y y w y y w y y y y w w y En y y w w1 1 3 15 w w y y 2 14 y y 1 13 En y y 12 w y y 1 3 11 w y y 2 10 y y 1 9 w 3 w y En y y 1 3 8 w w y 2 2 y 1 En En y w w y y 1 3 7 w y y 2 6 y y 1 5 En y y 4 w y y 1 3 3 w y y 2 2 y y 1 1 En y y

27. A 2-to-4 binary decoder LIBRARY ieee ; USE ieee.std_logic_1164.all ;
ENTITY dec2to4 IS
PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
En : IN STD_LOGIC ;
y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
END dec2to4 ;
ARCHITECTURE Dataflow OF dec2to4 IS
SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ;
BEGIN
Enw <= En & w ;
WITH Enw SELECT
y <= "0001" WHEN "100",
"0010" WHEN "101",
"0100" WHEN "110",
“1000" WHEN "111",
"0000" WHEN OTHERS ;
END Dataflow ;

28. VHDL code for Example 2 (1)
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY dec4to16 IS
PORT (w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
En : IN STD_LOGIC ;
y : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ) ;
END dec4to16 ;

29. VHDL code for Example 2 (2)
ARCHITECTURE Structure OF dec4to16 IS
COMPONENT dec2to4
PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
En : IN STD_LOGIC ;
y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
END COMPONENT ;
SIGNAL m : STD_LOGIC_VECTOR(3 DOWNTO 0) ;
BEGIN
Dec_r0: dec2to4 PORT MAP ( w(1 DOWNTO 0), m(0), y(3 DOWNTO 0) );
Dec_r1: dec2to4 PORT MAP ( w(1 DOWNTO 0), m(1), y(7 DOWNTO 4) );
Dec_r2: dec2to4 PORT MAP ( w(1 DOWNTO 0), m(2), y(11 DOWNTO 8) );
Dec_r3: dec2to4 PORT MAP ( w(1 DOWNTO 0), m(3), y(15 DOWNTO 12) );
Dec_left: dec2to4 PORT MAP ( w(3 DOWNTO 2), En, m ) ;
END Structure ;

30. VHDL code for Example 2 (2)
ARCHITECTURE Structure OF dec4to16 IS
COMPONENT dec2to4
PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
En : IN STD_LOGIC ;
y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
END COMPONENT ;
SIGNAL m : STD_LOGIC_VECTOR(3 DOWNTO 0) ;
BEGIN
G1: FOR i IN 0 TO 3 GENERATE
Dec_ri: dec2to4 PORT MAP ( w(1 DOWNTO 0), m(i), y(4*i+3 DOWNTO 4*i) );
END GENERATE ;
Dec_left: dec2to4 PORT MAP ( w(3 DOWNTO 2), En, m ) ;
END Structure ;

31. Up-or-down Free Running Counter
Example 3
Up-or-down Free Running Counter

32. Up-or-down Free Running Counter

33. Up-or-down Free Running Counter (1)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity up_or_down_counter is
generic(
WIDTH: natural:=4;
UP: natural:=0 );
port(
clk, reset: in std_logic;
q: out std_logic_vector(WIDTH-1 downto 0)
end up_or_down_counter;

34. Up-or-down Free Running Counter (2)
architecture mixed of up_or_down_counter is
signal r_reg: unsigned(WIDTH-1 downto 0);
signal r_next: unsigned(WIDTH-1 downto 0);
begin
-- register
process(clk,reset)
if (reset='1') then
r_reg <= (others=>'0');
elsif (clk'event and clk='1') then
r_reg <= r_next;
end if;
end process;

35. Up-or-down Free Running Counter (3)
-- next-state logic
inc_gen: -- incrementor
if UP=1 generate
r_next <= r_reg + 1;
end generate;
dec_gen: --decrementor
if UP/=1 generate
r_next <= r_reg – 1;
-- output logic
q <= std_logic_vector(r_reg);
end mixed;

36. Up-and-down Free Running Counter
Example 4
Up-and-down Free Running Counter

37. Up-and-down Free Running Counter

38. Up-and-down Free Running Counter (1)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity up_and_down_counter is
generic(WIDTH: natural:=4);
port(
clk, reset: in std_logic;
mode: in std_logic;
q: out std_logic_vector(WIDTH-1 downto 0) );
end up_and_down_counter;

39. Up-and-down Free Running Counter (2)
architecture arch of up_and_down_counter is
signal r_reg: unsigned(WIDTH-1 downto 0);
signal r_next: unsigned(WIDTH-1 downto 0);
begin
-- register
process(clk,reset)
if (reset='1') then
r_reg <= (others=>'0');
elsif (clk'event and clk='1') then
r_reg <= r_next;
end if;
end process;

40. Up-and-down Free Running Counter (3)
-- next-state logic
r_next <= r_reg + 1 when mode='1' else
r_reg - 1;
-- output logic
q <= std_logic_vector(r_reg);
end arch;

41. Example 5
Variable Rotator

42. Example 3: Variable rotator - Interface16 4 B
A <<< B 16 C

43. Block diagram

44. VHDL code for a 16-bit 2-to-1 Multiplexer
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY mux2to1_16 IS
PORT ( w0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
w1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s : IN STD_LOGIC ;
f : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ) ;
END mux2to1_16 ;
ARCHITECTURE dataflow OF mux2to1_16 IS
BEGIN
f <= w0 WHEN s = '0' ELSE w1 ;
END dataflow ;

45. Fixed rotation <<< 3 <<< 5
a(15) a(14) a(13) a(12) a(11) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0)
a(12) a(11) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0) a(15) a(14) a(13)
<<< 3
y <= a(12 downto 0) & a(15 downto 13);
a(15) a(14) a(13) a(12) a(11) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0)
a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0) a(15) a(14) a(13) a(12) a(11)
<<< 5
y <= a(10 downto 0) & a(15 downto 11);

46. Fixed rotation by L positions
a(15) a(14) a(13) a(12) a(11) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0)
a(15-L) a(15-L-1) a(1) a(0) a(15) a(14) a(15-L+2) a(15-L+1)
<<< L
y <= a(15-L downto 0) & a(15 downto 15-L+1);

47. VHDL code for for a fixed 16-bit rotator
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY fixed_rotator_left_16 IS
GENERIC ( L : INTEGER := 1);
PORT ( a : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
y : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ) ;
END fixed_rotator_left_16 ;
ARCHITECTURE dataflow OF fixed_rotator_left_16 IS
BEGIN
y <= a(15-L downto 0) & a(15 downto 15-L+1);
END dataflow ;

48. Structural VHDL code for for a variable 16-bit rotator (1)
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY variable_rotator_16 is
PORT(
A : IN STD_LOGIC_VECTOR(15 downto 0);
B : IN STD_LOGIC_VECTOR(3 downto 0);
C : OUT STD_LOGIC_VECTOR(15 downto 0) );
END variable_rotator_16;

49. Structural VHDL code for for a variable 16-bit rotator (2)
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ARCHITECTURE structural OF variable_rotator_16 IS
COMPONENT mux2to1_16
PORT ( w0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
w1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s : IN STD_LOGIC ;
f : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ) ;
END COMPONENT ;
COMPONENT fixed_rotator_left_16
GENERIC ( L : INTEGER := 1);
PORT ( a : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
y : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ) ;

50. Structural VHDL code for for a variable 16-bit rotator (3)
TYPE array1 IS ARRAY (0 to 4) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
TYPE array2 IS ARRAY (0 to 3) OF STD_LOGIC_VECTORS(15 DOWNTO 0);
SIGNAL Al : array1;
SIGNAL Ar : array2;
BEGIN
Al(0) <= A;
G: FOR i IN 0 TO 3 GENERATE
ROT_I: fixed_rotator_left_16
GENERIC MAP (L => 2** i)
PORT MAP ( a => Al(i) ,
y => Ar(i));
MUX_I: mux2to1_16 PORT MAP (w0 => Al(i),
w1 => Ar(i),
s => B(i),
f => Al(i+1));
END GENERATE;
C <= Al(4);
END variable_rotator_16;

51. Block diagram

52. Example 6
XOR Tree

53. XOR Tree

54. XOR Tree (1) library ieee; use ieee.std_logic_1164.all;
use work.util_pkg.all;
entity reduced_xor is
generic(WIDTH: natural:=8);
port(
a: in std_logic_vector(WIDTH-1 downto 0);
y: out std_logic );
end reduced_xor;
architecture gen_tree_arch of reduced_xor is
constant STAGE: natural:= log2c(WIDTH);
signal p: std_logic_2d(STAGE downto 0, WIDTH-1 downto 0);

55. XOR Tree (2) begin -- rename input signal in_gen:
for i in 0 to (WIDTH-1) generate
p(STAGE, i) <= a(i);
end generate;
-- replicated structure
stage_gen:
for s in (STAGE-1) downto 0 generate
row_gen:
for r in 0 to (2**s-1) generate
p(s, r) <= p(s+1, 2*r) xor p(s+1, 2*r+1);
-- rename output signal
y <= p(0, 0);
end gen_tree_arch;

56. util_pkg (1) library ieee; use ieee.std_logic_1164.all;
package util_pkg is
type std_logic_2d is
array(integer range <>, integer range <>) of std_logic;
function log2c (n: integer) return integer;
end util_pkg ;

57. util_pkg (2) --package body package body util_pkg is
function log2c(n: integer) return integer is
variable m, p: integer;
begin
m := 0;
p := 1;
while p < n loop
m := m + 1;
p := p * 2;
end loop;
return m;
end log2c;
end util_pkg;

58. Array Data Type Array Type
TYPE data_type_name IS ARRAY (range_1, range2, ...)
OF element_data_type;

59. XOR Tree with Arbitrary Input Size (1)
begin
-- rename input signal
in_gen:
for i in 0 to (WIDTH-1) generate
p(STAGE,i) <= a(i);
end generate;
-- padding 0’s
pad0_gen:
if WIDTH < (2**STAGE) generate
zero_gen:
for i in WIDTH to (2**STAGE-1) generate
p(STAGE,i) <= '0’;

60. XOR Tree with Arbitrary Input Size (2)
-- replicated structure
stage_gen:
for s in (STAGE-1) downto 0 generate
row_gen:
for r in 0 to (2**s-1) generate
p(s,r) <= p(s+1,2*r) xor p(s+1,2*r+1);
end generate;
-- rename output signal
y <= p(0,0);
end gen_tree2_arch;

61. Unconstrained Array Types
ECE 545 – Introduction to VHDL

62. Predefined Unconstrained Array Types
bit_vector array of bits
string array of characters
ECE 545 – Introduction to VHDL

63. Predefined Unconstrained Array Types
Defined in the std_logic_1164 package:
type std_logic_vector is array (natural range <>)
of std_logic;
Defined in the numeric_std package:
type unsigned is array (natural range <>)
of bit;
type signed is array (natural range <>)

64. Using Predefined Unconstrained Array Types
subtype byte is bit_vector(7 downto 0); ….
signal channel_busy : bit_vector(1 to 4);
constant ready_message : string := “ready”;
signal memory_bus: std_logic_vector (31 downto 0);

65. User-defined Unconstrained Array Types
type std_logic_2d is
array(integer range <>, integer range <>) of std_logic;
signal s1: std_logic_2d(3 downto 0, 5 downto 0);
signal s2: std_logic_2d(15 downto 0, 31 downto 0);
signal s3: std_logic_2d(7 downto 0, 1 downto 0);

66. User-defined Unconstrained Array Type in a package
use work.util_pkg.all;
entity ….
generic (
ROW: natural;
COL: natural) );
port (
p1: in std_logic_2d(ROW-1 downto 0, COL-1 downto 0);
…….. )
architecture
signal s1: std_logic_2d(ROW-1 downto 0, COL-1 downto 0);

67. Array-of-Arrays Data Type
constant ROW : natural := 4;
constant COL : natural := 6;
type sram_row_by_col is array (ROW -1 downto 0) of
std_logic_vector(COL – 1 downto 0); ……
signal t1: sram_row_by_col;
signal v1: std_logic_vector(COL-1 downto 0);
signal b1: std_logic;
t1 <= (“000101”, “101001”, others => (others => ‘0’));
b1 <= t1(3)(0);
v1 <= t1(2);

68. Aliases
ECE 448 – FPGA and ASIC Design with VHDL

69. Aliases Example: Syntax: ALIAS name : type := expression;
signal IR : std_logic_vector(31 downto 0);
alias IR_opcode : std_logic_vector(5 downto 0) is IR(31 downto 26);
alias IR_reg1_addr : std_logic_vector(4 downto 0) is IR(25 downto 21);
alias IR_reg2_addr : std_logic_vector(4 downto 0) is IR(20 downto 16);

70. Attributes of Arrays and Array Types
ECE 545 – Introduction to VHDL

71. Array Attributes
A’left(N) left bound of index range of dimension N of A
A’right(N) right bound of index range of dimension N of A
A’low(N) lower bound of index range of dimension N of A
A’high(N) upper bound of index range of dimension N of A
A’range(N) index range of dimension N of A
A’reverse_range(N) reversed index range of dimension N of A
A’length(N) length of index range of dimension N of A
A’ascending(N) true if index range of dimension N of A
is an ascending range, false otherwise

72. Array Attributes - Examples
type A is array (1 to 4, 31 downto 0);
A’left(1) = 1
A’right(2) = 0
A’low(1) = 1
A’high(2) = 31
A’range(1) = 1 to 4
A’length(2) = 32
A’ascending(2) = false

73. Unconstrained PARITY Generator (1)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY parity IS
PORT(
parity_in : IN STD_LOGIC_VECTOR;
parity_out : OUT STD_LOGIC );
END parity;

74. Unconstrained PARITY Generator (2)
ARCHITECTURE parity_dataflow OF parity IS
CONSTANT width: natural := parity_in’length;
SIGNAL xor_out: STD_LOGIC_VECTOR (width-1 DOWNTO 0);
BEGIN
xor_out(0) <= parity_in(0);
G2: FOR i IN 1 TO 7 GENERATE
xor_out(i) <= xor_out(i-1) XOR parity_in(i);
END GENERATE G2;
parity_out <= xor_out(width-1);
END parity_dataflow;

75. Unconstrained PARITY Generator (3)
Will the previous code work for the following
types of signal parity_in?
std_logic_vector(7 downto 0);
std_logic_vector(0 to 7);
std_logic_vector(15 downto 8);
std_logic_vector(8 to 15);

76. Unconstrained PARITY Generator (4)
ARCHITECTURE parity_dataflow OF parity IS
CONSTANT width: natural := parity_in’length;
SIGNAL xor_out: STD_LOGIC_VECTOR (width-1 DOWNTO 0);
SIGNAL pp: STD_LOGIC_VECTOR (width-1 DOWNTO 0);
BEGIN
pp <= parity_in;
xor_out(0) <= pp(0);
G2: FOR i IN 1 TO 7 GENERATE
xor_out(i) <= xor_out(i-1) XOR pp(i);
END GENERATE G2;
parity_out <= xor_out(width-1);
END parity_dataflow;

77. Subprograms
ECE 545 – Introduction to VHDL

78. Subprograms Include functions and procedures
Commonly used pieces of code
Can be placed in a library, and then reused and shared among various projects
Abstract operations that are repeatedly performed
Type conversions
Use only sequential statements, the same as processes
ECE 545 – Introduction to VHDL

79. Typical locations of subprograms
PACKAGE
PACKAGE BODY
LIBRARY
global
ENTITY
FUNCTION /
PROCEDURE
local for all architectures
of a given entity
ARCHITECTURE
Declarative part
local for a given architecture
ECE 545 – Introduction to VHDL

80. Functions
ECE 545 – Introduction to VHDL

81. Functions – basic features
always return a single value as a result
Are called using formal and actual parameters the same way as components
never modify parameters passed to them
parameters can only be constants (including generics) and signals (including ports);
variables are not allowed; the default is a CONSTANT
when passing parameters, no range specification should be included (for example no RANGE for INTEGERS, or TO/DOWNTO for STD_LOGIC_VECTOR)
are always used in some expression, and not called on their own
ECE 545 – Introduction to VHDL

82. Function syntax FUNCTION function_name (<parameter_list>)
RETURN data_type IS
[declarations]
BEGIN
(sequential statements)
END function_name;
ECE 545 – Introduction to VHDL

83. Function parameters - example
FUNCTION f1
(a, b: INTEGER; SIGNAL c: STD_LOGIC_VECTOR)
RETURN BOOLEAN IS
BEGIN
(sequantial statements)
END f1;
ECE 545 – Introduction to VHDL

84. Function calls - examples
b <= to_boolean(s);
x <= conv_integer(a);
IF x > maximum(a, b) THEN ....
WHILE minimum(a, b) LOOP
ECE 545 – Introduction to VHDL

85. Function – Example 1 LIBRARY ieee; USE ieee.std_logic_1164.all;
FUNCTION to_boolean (a: std_logic) RETURN boolean IS
VARIABLE result : boolean;
BEGIN
IF (a=‘1’) THEN
result := true;
ELSE
result := false;
END IF;
RETURN result;
END to_boolean;
ECE 545 – Introduction to VHDL

86. Function – Example 2 LIBRARY ieee; USE ieee.std_logic_1164.all;
PACKAGE my_package IS
FUNCTION log2_ceil (CONSTANT s: INTEGER) RETURN INTEGER;
END my_package;
PACKAGE body my_package IS
FUNCTION log2_ceil (CONSTANT s: INTEGER) RETURN INTEGER IS
VARIABLE m,n : INTEGER;
BEGIN
m := 0;
n := 1;
WHILE (n < s) LOOP
m := m + 1;
n := n*2;
END LOOP;
RETURN m;
END log2_ceil;
ECE 545 – Introduction to VHDL

87. Function call – Example 2
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE work.my_package.all;
ENTITY log2_int IS
GENERIC (m: INTEGER :=20);
PORT (x: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
y: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );
END log2_int;
ARCHITECTURE log2_int OF log2_int IS
CONSTANT l2m : INTEGER := log2_ceil (m);
SIGNAL r : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
r <= conv_std_logic_vector(l2m,4);
y <= x*r;
ECE 545 – Introduction to VHDL

88. Function – Example 3
function rorx ( signal x : std_logic_vector; y : integer)
return std_logic_vector is
begin
return (x(y-1 downto x'low) & x(x'high downto y));
end rorx;
ECE 545 – Introduction to VHDL

89. Function – Example 4
function shrx ( signal x : std_logic_vector; y : integer) return std_logic_vector is
variable zeros: std_logic_vector(y-1 downto 0)
:= (others => '0');
begin
return (zeros & x(x'high downto y));
end shrx;
ECE 545 – Introduction to VHDL

90. Package containing a function (1)
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
PACKAGE sha3_pkg IS
function shrx ( x : std_logic_vector; y : integer) return std_logic_vector;
function rorx ( x : std_logic_vector; y : integer) return std_logic_vector;
END sha3_pkg
ECE 545 – Introduction to VHDL

91. Package containing a function (2)
PACKAGE BODY sha3_pkg IS
function rorx ( signal x : std_logic_vector; y : integer)
return std_logic_vector is
begin
return (x(y-1 downto x'low) & x(x'high downto y));
end rorx;
function shrx ( signal x : std_logic_vector; y : integer)
variable zeros: std_logic_vector(y-1 downto 0) := (others => '0');
return (zeros & x(x'high downto y));
end shrx;
END PACKAGE BODY sha3_pkg
ECE 545 – Introduction to VHDL

92. Using a Package library ieee; use ieee.std_logic_1164.all;
use work.sha3_pkg.all;
ENTITY shift_and_rotate IS
PORT ( a: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
b: OUT STD_LOGIC_VECTOR (15 DOWNTO 0));
END conv_int2;
ARCHITECTURE my_arch OF shift_and_rotate IS
SIGNAL tmp : STD_LOGIC_VECTOR (15 DOWNTO 0);
BEGIN
tmp <= rorx(a, 4);
b <= shrx(tmp, 5);
END my_arch;
ECE 545 – Introduction to VHDL

93. Type conversion function (1)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE my_package IS
FUNCTION conv_integer (SIGNAL vector: STD_LOGIC_VECTOR)
RETURN INTEGER;
END my_package;
ECE 545 – Introduction to VHDL

94. Type conversion function (2)
PACKAGE BODY my_package IS
FUNCTION conv_integer (SIGNAL vector: STD_LOGIC_VECTOR)
RETURN INTEGER;
VARIABLE result: INTEGER RANGE 0 TO 2**vector’LENGTH - 1;
VARIABLE carry: STD_LOGIC;
BEGIN
IF(vector(vector’HIGH)=‘1’ THEN result:=1;
ELSE result := 0;
FOR i IN (vector’HIGH-1) DOWNTO (vector’LOW) LOOP
result := result*2;
IF (vector(i) = ‘1’) THEN result := result+1;
END IF;
RETURN result;
END conv_integer;
END my_package;
ECE 545 – Introduction to VHDL

95. Type conversion function (3)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.my_package.all;
ENTITY conv_int2 IS
PORT ( a: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
y: OUT INTEGER RANGE 0 TO 15);
END conv_int2;
ARCHITECTURE my_arch OF conv_int2 IS
BEGIN
y <= conv_integer(a);
END my_arch;
ECE 545 – Introduction to VHDL

96. Procedures
ECE 545 – Introduction to VHDL

97. Procedures – basic features
do not return a value
are called using formal and actual parameters the same way as components
may modify parameters passed to them
each parameter must have a mode: IN, OUT, INOUT
parameters can be constants (including generics), signals (including ports), and variables; the default for inputs (mode in) is a constant, the default for outputs (modes out and inout) is a variable
when passing parameters, range specification should be included (for example RANGE for INTEGERS, and TO/DOWNTO for STD_LOGIC_VECTOR)
Procedure calls are statements on their own
ECE 545 – Introduction to VHDL

98. Procedure syntax PROCEDURE procedure_name (<parameter_list>) IS
[declarations]
BEGIN
(sequential statements)
END function_name;
ECE 545 – Introduction to VHDL

99. Procedure calls - examples
parity(parity_in, parity_out);
compute_min_max(in1, in2, in3, out1, out2);
divide(dividend, divisor, quotient, remainder);
IF (a > b) THEN
ECE 545 – Introduction to VHDL

100. Procedure – example procedure PARITY (signal X : in std_logic_vector;
signal Y : out std_logic) is
variable TMP : std_logic := '0';
begin
for J in X'range loop
TMP := TMP xor X(J);
end loop; -- works for any size X
Y <= TMP;
end PARITY;
ECE 545 – Introduction to VHDL

101. Procedure defined in a package
package REF_PACK is
procedure PARITY
(signal X : in std_logic_vector;
signal Y : out std_logic);
end REF_PACK;
package body REF_PACK is
signal Y : out std_logic) is
begin
for J in X'range loop
TMP := TMP xor X(J);
end loop; -- works for any size X
Y <= TMP; end PARITY;
ECE 545 – Introduction to VHDL