1. Lab. 4 – Part 1 Demonstrating and understanding multi-processor boot
TigerSHARC multi-processor system

2. Overview
Lab. 4 Task 1– Generating and testing tasks for a multi-processor system
Lab. 4 Task 2 – Demonstrating multi-processor boot
Lab. 4 Task 3 -- Read the flags (button) from each processor and deactivate the sound from that processor (FLAG0_A deactivates left channel – FLAG0_B deactivate right channel)
Understanding new TigerSHARC functionality
Understanding TigerSHARC multi-processor bus arbitration
Understanding TigerSHARC boot-process
1/12/2019
TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

3. Blackfin ADSP-BF533 “Conventional approach”
What does “booting” the processor require and why is it necessary?
On power up, the processor “knows” nothing.
Need a systematic and reliable mechanism to “configure” the system.
Essentially put registers into known state
Move code from an external (8-bit wide) EPROM or FLASH memory to faster memory for easier execution
Jump to the new code
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TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

4. Blackfin boot procedure starts with code from “on chip” boot rom
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TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

5. TigerSHARC – more complicated as multi-processor
Simple example
Copy AudioTalkThrough C directory as Lab4/LeftCode and Lab4/RightCode
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TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

6. Rename .prj as LeftCode.dpj ditto the project name
Repeat for Right
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TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

7. Lab. 4 Tasks 1, 2 and 3 continued
Check that the new LeftCode project works as expected
Repeat for RightCode project
Long Term plan
Modify Right Code project to produce only left sound – download into DSPA
Modify Left Code project to produce only left sound – download into DSPB
Check whether working or not
Generate a boot file that enable us to select which of several .dxe will execute
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TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

8. Expected project configuration Now modify “Audio.c” file
Remove WriteDataRight from LeftCode
Remove WriteDataLeft from RightCode
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TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

9. Testing the code From Left Code project From Right Code project
Download LeftCode/Debug/MainA.dxe into DSPA
Download LeftCode/Debug/MainB.dxe into DSPB
Activate both processors – hear left channel only
From Right Code project
Download RightCode/Debug/MainA.dxe into DSPA
Download RightCode/Debug/MainB.dxe into DSPB
Activate both processors – hear right channel only
Download RightCode/Debug/MainA.dxe into DSPB
Activate DSPA only – hear left channel only
Activate both DSPA and DSPB – hear both channels
Note that this is “more good luck” than skilled programming. However, it is demonstrating how the two processors are arbitrating bus access to the audio A/D and D/A chips
1/12/2019
TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

10. Two different TigerSHARC dxe in each of the processors
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TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

11. Need to build a loader (.ldr) file for storing in FLASH
The default approach of setting project options to build a “loader” file (.ldr) rather than “executable” file (.dxe) does not work as we are dealing with multi-processor
I consider this is as a bug in the IDDE
Need to do this by hand
1/12/2019
TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

12. Build a loader.bat file on your desktop
Build a .txt file, change name to loader.bat, then use “edit” and NOT “open”
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TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

13. Use a cmd window to produce .ldr
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TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

14. Now flash the EEPROM 2 1
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TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

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TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

16. Disconnect VDSP from the target (or exit from VDSP)
Disconnect VDSP from the target (or exit from VDSP). Power cycle the board
On re power – you should hear program running.
Modify the Audio.c code so that you can read the Flag0 flag for that processor. If Flag is set – then do-not output any sound
1/12/2019
TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

17. Understanding the TigerSHARC flag register
Resets as “input” – Why that reset?
LED is connected as output Need to enable as out
Need to read bit then echo result to LED
1/12/2019
TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

18. Flag control via “C”
volatile long int *pFLAGREG = (volatile long int *) 0x1E0354;
volatile long int *pFLAGREG_W1S = (volatile long int *) 0x1E0355;
volatile long int *pFLAGREG_W1C = (volatile long int *) 0x1E0356;
long int flagValueBit = *pFLAGREG & 0x1;
Careful – one of the LED output is being used to control the RESET on the audio
1/12/2019
TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

19. Bus Arbitration
We have two processors accessing one external memory location (for both read and there is no conflict.
How does the bus arbitration work on the TigerSHARC
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TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

20. From TigerSHARC hardware manual
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TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

21. From TigerSHARC hardware manual
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TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

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TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

23. Multi- TigerSHARC cluster
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TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

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TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

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TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

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TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

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TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

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TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada

29. Overview
Lab. 4 Task 1– Generating and testing tasks for a multi-processor system
Lab. 4 Task 2 – Demonstrating multi-processor boot
Lab. 4 Task 3 -- Read the flags (button) from each processor and deactivate the sound from that processor (FLAG0_A deactivates left channel – FLAG0_B deactivate right channel)
Understanding new TigerSHARC functionality
Understanding TigerSHARC multi-processor bus arbitration
Understanding TigerSHARC boot-process
1/12/2019
TigerSHARC Lab , Copyright M. Smith, ECE, University of Calgary, Canada