1. Chapter 1

2. Analysis versus design
Given a system, find its properties.
The solution is unique.
Design:
Given a set of properties, come up with a system possessing them.
The solution is rarely unique.

3. Texas Instruments, or Vaibhav Kumar’s view

4. Electrical Design
the process from the specifications to a circuit solution
Requires active and passive
device electrical models for
Creating the design
Verifying the design
Determining the robustness of the design

5. Physical Design
From electrical design to a layout pattern

6. Signal naming conventions

7. Appendix A

8. Circuit analysis skills
Please review materials in appendix A
Make sure you are fluent at
Nodal analysis, KCL
Mesh analysis (dual to nodal), KVL
Cascade stages
Small signal analysis, including linearization
Equivalent circuits, Thevenin, Norton
Miller simplification
Use google or wiki, if needed

9. Small signal analysis
The amplifier may be nonlinear, but near an operating point, it has a small signal model of: vo = Av * vin.
By definition, SSA is always linear.

10. Making
Equivalent
substitutions
Simplified
Cascade

11. Miller simplification
If v2 = K*v1
i1 = (v1-Kv1)/Z
=(1-K)v1/Z
i2 = (v2-v1/K)/Z
=(K-1)/K v2/Z

12. 1/sC v1 v1 _ + _ + v2 A A ? v2 ?
K=?

13. Chapter 2

14. BASIC FABRTICATION PROCESSES
Oxide growth
Thermal diffusion
Ion implantation
Deposition
Etching
Shallow trench isolation
Epitaxy
Photolithography
CMP

15. Oxidation
The process of growing a layer of silicon dioxide (SiO2)on the surface of a silicon wafer.
Uses:
Provide isolation between two layers
Protect underlying material from contamination
Very thin oxides (100 to 1000 Å) are grown using dry-oxidation techniques.
Thicker oxides (>1000 Å) are grown using wet oxidation techniques.

16. (Thickness of SiO2 grossly exaggerated.)

17. Diffusion
Movement of impurity atoms at the surface of the silicon into the bulk of the silicon
From higher concentration to lower concentration.
Done at high temperatures: 800 to 1400 °C.

19. Infinite-source diffusion

20. Finite-source diffusion

21. Ion Implantation
The process by which impurity ions are accelerated to a high velocity and physically lodged into the target.

22. Require annealing to repair damage
Can implant through surface layers
Can achieve unique doping profile

23. Deposition Chemical-vapor deposition (CVD)
Low-pressure chemical-vapor deposition
Plasma-assisted chemical-vapor deposition
Sputter deposition
Materials deposited
Silicon nitride (Si3N4)
Silicon dioxide (SiO2)
Aluminum
Polysilicon

24. Etching To selectively remove a layer of material
But may remove portions or all of
The desired material
The underlying layer
The masking layer
Two basic types of etches:
Wet etch, uses chemicals
Dry etch, uses chemically active ionized gasses.

25. Wet etching
Wet Etching

26. Selectivity: Anisotropy: a and b due to finite S
c is due to non-unity A

27. Epitaxy
Epitaxial growth consists of the formation of a layer of single-crystal silicon on the surface of the silicon material so that the crystal structure of the silicon is continuous across the interfaces.
It is done externally to the material as opposed to diffusion which is internal
The epitaxial layer (epi) can be doped differently, even opposite to the material on which it is grown
It is accomplished at high temperatures using a chemical reaction at the surface
The epi layer can be any thickness, typically 1-20 microns

28. Photolithography Components Positive photoresist-
Photoresist material
Photomask
Material to be patterned (e.g., SiO2)
Positive photoresist-
Areas exposed to UV light are soluble in the developer
Negative photoresist-
Areas not exposed to UV light are soluble in the developer

29. Steps: 1. Apply photoresist 2. Soft bake
3. Expose the photoresist to UV light through photomask
4. Develop (remove unwanted photoresist)
5. Hard bake
6. Etch the exposed layer
7. Remove photoresist

30. Expose: The process of exposing selective areas to light
through a photo-mask is
called printing.
Types of printing include:
• Contact printing
• Proximity printing
• Projection printing

31. After Developing

32. After Etching

33. After Removing Photoresist

34. CMOS Technology Flow varies with process types & company
N-Well CMOS (EE330, 435, overview below)
Twin-Well CMOS (overview in 2.1)
STI (for deep submicron, overview below)
Start with substrate selection
Type: n or p
Doping level, →resistivity
Orientation, 100, or 101, etc
Other parameters

35. N-well CMOS (ON.5um) pMOS transistors in n-well
nMOS transistors on substrate
nMOS transistor’s body is always connected to lowest voltage of chip
nMOS is a three terminal device
pMOS body can be tied to voltages other than Vdd
pMOS is a four terminal device
0.35um and larger typically n-well

36. VDD M2
Vin Vo M1

37. Major n-well CMOS Steps

38. Major n-well CMOS Steps

39. Major n-well CMOS Steps

40. Major n-well CMOS Steps

41. Major n-well CMOS Steps

42. Major n-well CMOS Steps

43. Major n-well CMOS Steps

44. Major n-well CMOS Steps

45. Relative size of different layers

46. For twin well process step for the same inverter, refer to the book.

47. Deep SubMicron Challenges
Transistor sizes become very small
But FOX lateral size cannot be reduced
Depletion region between p-well and n-well not reduced
Large area
FOX
depletion

49. Shallow Trench Isolation Technology
Allowing transistors to be spaced closer

50. Shallow Trench Isolation (STI)
Cover the wafer with pad oxide and silicon nitride.
First etch nitride and pad oxide. Next, an anisotropic etch is made in the silicon to a depth of 0.4 to 0.5 microns.
Grow a thin thermal oxide layer on the trench walls.
A CVD dielectric film is used to fill the trench.
A chemical mechanical polishing (CMP) step is used to polish back the dielectric layer until the nitride is reached. The nitride acts like a CMP stop layer.
Densify the dielectric material at 900°C and strip the nitride and pad oxide.