1. CPE/EE 428, CPE 528 Testing Combinational Logic (3)
Department of Electrical and Computer Engineering University of Alabama in Huntsville

2. Testing Digital Systems
Combinational vs Sequential Systems
We shall cover combinational first
Sequential circuits can be tested using combinational test generation and scan chains
The state FF’s are connected in a shift register. Any value can be shifted in (setting an arbitrary state), the next state loaded, and then shifted out. Thus tests can be directly applied to the combinational logic. d Q …
Combinational
logic
FF’s
load enable/shift
scan chain shiftin/out
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VLSI Design II: VHDL

3. Testing Digital Systems: Detectionx
Z(x)
A good circuit N produces function Z(x)
A circuit with fault f produces a different function Z f (x) x
Z f (x)
N f
Detecting a fault
A test vector t is an assignment of input values. It detects a fault f iff Z(t)  Z f (t)
The set of all tests {T} that detects f is found by Z(x)  Z f (x) = 1
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VLSI Design II: VHDL

4. Testing Digital Systems: Detection
Assume x4 s-a-0 (stuck-at 0, sa0) x2 x3 x1
Good Circuit Z x4 x2 x3 x1
Faulty Circuit Zf
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VLSI Design II: VHDL

5. Testing Digital Systems: Detection
test for x4 s-a-0 x2
(a+b)  a = ?
= (a+b) a’ + (a+b)’ a
= aa’ + a’b + (a’ • b’) a
= a’b
= ((x2+x3)x1)’ • x1’x4
= (cx1)’ • x1’x4
= (c’ + x1’) • x1’x4
= c’x1’x4 + x1’x4
= x1’x4 x3 x1 Z x4
Z(x)  Z f (x) = 1
Z = (x2 + x3) x1 + x1’x4
Z f = (x2 + x3) x1
 —> x1’x4 = 1
This says that any input vector with x1 = 0 and x4 = 1 is a test vector for x4 s-a-0. x2 and x3 are don’t-cares.
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VLSI Design II: VHDL

6. Testing Digital Systems: Detectionx2 x3
test for x4 s-a-0 x1
1/0 Z 1 1 x4
1/0
1/0
s-a-0
The combined good/bad circuit can be drawn
values shown are for v/vf
that is, values in the good circuit / values in the faulty circuit
v/vf shows a discrepancy between good/faulty circuit values
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VLSI Design II: VHDL

7. Fault Activation and Propagationx2 x3 x1
1/0 Z
test for x4 s-a-0 1 1 x4
1/0
1/0
s-a-0
Two basic concepts in fault detection illustrated
A test must activate the fault by creating different v/vf values at the fault site
thus x4 is assigned to be 1. If it really is stuck at zero, we know there will be a change in circuit values.
A test must propagate the error to a primary output
other circuit values must be selected to allow the good/faulty value to be seen at an output.
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VLSI Design II: VHDL

8. Path Sensitization Path sensitization x2 x3 x1 1/0 Z test for x4 s-a-0x1
1/0 Z
test for x4 s-a-0 1 1 x4
1/0
1/0
Sensitized path
s-a-0
Path sensitization
A line whose value (with the test t) changes in the presence of fault f is said to be sensitized to fault f by test t
these lines are indicated by having different v/vf values
A path composed of sensitized lines is a sensitized path
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VLSI Design II: VHDL

9. Another example Test x1 s-a-0 x2 x3 x1 Z x4 s-a-0 13/01/2019
VLSI Design II: VHDL

10. Controlling and Inverting Values
Aside
Primitive logic gates (AND, OR, NAND, NOR) can be characterized by two parameters
controlling value — c
inversion — i
Controlling value
the value when on any one input will determine the gate’s output regardless of the other inputs
(e.g. 0 on any AND gate input)
If one input has the controlling value, the gate’s output will be
c  i, where c and i come from the following table
c i
AND 0 0
OR 1 0
NAND 0 1
NOR 1 1
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VLSI Design II: VHDL

11. Controlling and Inverting Values
Along the sensitized path
any input sensitized to the fault will have a value, call it d
all other inputs will have c’ (complement of controlling value)
a non-controlling, or enabling, value
the output will have value d  i d d’
c i
AND 0 0
OR 1 0
NAND 0 1
NOR 1 1 1 d d d
could be 1/0 or 0/1
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VLSI Design II: VHDL

12. Controlling and Inverting Valuesx2 x3
c i
AND 0 0
OR 1 0
NAND 0 1
NOR 1 1 x1
1/0 Z 1 1 x4
1/0
1/0
s-a-0
Which are controlling, which are enabling?
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VLSI Design II: VHDL

13. Testing Digital Circuits: Redundancy
Fault f is detectable if there exists a test t that detects it i.e. Z(t)  Z f (t)
However, f is undetectable if Z(x) = Z f (x) for all x
Cool! There are some circuits where even if there is a fault in certain places, they still work!
A circuit that contains an undetectable fault is a redundant circuit.
The fault site obviously has no effect on the circuit function
The circuit can be simplified — you can remove something!
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VLSI Design II: VHDL

14. Testing Digital Circuits: RedundancyX b Y F c Z
Example:
F = ab + bc + a’c
Is the fault Y s-a-0 detectable?
Activate and propagate Y s-a-0
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VLSI Design II: VHDL

15. Redundancy Y s-a-0 is undetectable Change to circuit
F = ab + bc + a’c = ab + a’c
The term bc is a redundant cover in the Kmap
it’s not an essential implicant of the function — the other two are
Change to circuit
Gate Y can be removed from the circuit without affecting the logic function.
Or you can keep it and have some fault tolerance 1 ab c
term bc is redundant a b c X Y Z
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VLSI Design II: VHDL

16. Redundancy — Pro and Con
The fault is undetectable.
This can be good! The circuit still works even if there are certain faults in it.
Are others undetectable too? — or harder to detect
The redundant circuit requires extra hardware — extra area on the IC
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VLSI Design II: VHDL

17. Redundancy — Pro and Con
The circuit is hazard free on transition 111 —> 011
Hazard — the value of the function takes on an intermediate value different from the final value
With a non-redundant circuit, there is a chance of a hazard
With the redundant circuit, if the inputs change from 111 —> 011, the output will not go to zero. Are there other such transitions? 1 ab c x z a X b Y c Z
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VLSI Design II: VHDL

18. Testing Digital Circuits: Redundancy
Removing redundant covers
Other redundancies
Triple modular redundancy — a method for achieving fault tolerance.
faults are correct by additional logic
many faults would be untestable — they’d be automatically corrected
… and logic synthesis would optimize the redundancy away!
Need a test mode to disable correction
Undetectable fault Simplification Rule
AND (NAND) input s-a-1 Remove input
AND (NAND) input s-a-0 Remove gate, replace by 0 (1)
OR (NOR) input s-a-0 Remove input
OR (NOR) input s-a-1 Remove gate, replace by 1 (0)
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VLSI Design II: VHDL

19. Testing: is it so simple?
Test engineers = Sherlock Holmes of the industry
Methods for automatically generating tests were necessary
Collectively known as ATPG => Automatic Test Pattern Generation
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VLSI Design II: VHDL

20. D-Calculus
D (Detect) = 1/0 - represents a logic 1 in the good circuit and a logic 0 in the bad circuit
D (Dbar) = 0/1 - represents a logic 0 in the good circuit and a logic 1 in the bad circuit
Five-valued logic: 0, 1, D, Dbar, X (don’t care)
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VLSI Design II: VHDL

21. D-Calculus Truth tables for AND, OR, NAND, and NOR gates 13/01/2019
VLSI Design II: VHDL

22. Definitions Test generation algorithms work in terms of:
Primary inputs — (PI) a controllable input to a circuit. E.g., a pin on an IC, or an output of an FF in a scan system
Primary outputs — (PO) an observable output of the circuit. E.g., a pin on an IC, or a D input to an FF in a scan system
Justify, justification — the process of selecting PIs to force a certain line to have a specific value
Propagate, propagation — the process of selecting appropriate PIs that allow a discrepancy “D” to be pushed to a PO
Test generation algorithms are all about
finding the appropriate PIs to control to activate a fault
finding the appropriate PIs to control to propagate the fault to one of the POs.
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VLSI Design II: VHDL

23. More Definitions Forward implication Backward implication
Def: Knowing one or more gate inputs, imply the output value.
Assume all gate inputs are the same value — either all c or all c’
Then the output is
output = value  i
We can refine this if we know the controlling value
i.e. only one of the inputs needs to have c to know output
Backward implication
Def: Knowing the output and possibly some inputs, imply one or more of the inputs
Assume all gate inputs are the same — either all c or c’
Then the inputs are:
inputs = output  i
If the input needed to produce the output is c, then only one input needs to have it.
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VLSI Design II: VHDL

24. Justify Algorithm
Justify (l , v) — Recursive algorithm to justify line l to value v
l = v
if l is a primary input return — you’re done on this path
set c and i to controlling/inversion values of gate driving l
inval = v  i
if (inval == c)
select one input j of gate l
Justify (j, inval)
else
for every input j of gate l l 1 x
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VLSI Design II: VHDL

25. An example of justification
l = v
if l is a primary input return — you’re done on this path
set c and i to controlling/inversion values of gate driving l
inval = v  i
if (inval == c)
select one input j of gate l
Justify (j, inval)
else
for every input j of gate l
justify a to 1 a PO B
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VLSI Design II: VHDL

26. Test Generation: Propagate Algorithm
Prop (l , err) — Propagate value err from line l
l = err
if line l is a primary output return — you’re home
k = fanout gate of line l
c,i = controlling/inversion value of gate k
for every input j of k other than l
Justify (j, c’)
Propagate (k, err  i) l k
Justify enabling values onto other inputs
Propagate
further
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VLSI Design II: VHDL

27. Testing Digital Circuits
What you know
Fault models — what can go wrong and how we model it
physical and logical
Basic idea of detection — activate fault and propagate to output
What you don’t know
how to figure out, systematically, whether the whole thing works
how to reduce the number of faults to consider when generating tests
Today
Review equivalence and fault collapsing
Begin test generation algorithms
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VLSI Design II: VHDL

28. Detection Basic approach seen so far
Select a line and a fault — line l s-a-v
Activate the fault
Drive line l to v’ — selecting the inputs needed to set an internal line to a known value is known as line justification
Activation creates a discrepancy “D”
Propagate the fault
Propagate the discrepancy D along a sensitized path to any primary output
discrepancy
s-a-0
1/0
Notation: good value/bad value x
0/1 1
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VLSI Design II: VHDL

29. Fault Dominance Equivalence vs. Dominance Dominance
Dominance is a special case of fault equivalence
Fault equivalence, if Z f (x) = Z g (x) for all x then the faults are functionally equivalent.
If this is true for a subset of x, then there is a dominance relation
Dominance
Let Tg be the set of all tests that detect a fault g.
A fault f dominates the fault g iff f and g are functionally equivalent under Tg.
Z f (t) = Z g (t) for all t in Tg
Tg is a subset of Tf
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VLSI Design II: VHDL

30. Equivalence and Dominance Summary
What are the equivalence classes?
s-a-0
s-a-1
Equivalence
A0, B0, Z1
s-a-0
s-a-1
s-a-0
s-a-1
Dominance
Z0 dominates A1, B1
11, 01, 10
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VLSI Design II: VHDL

31. Aside: Fault Location Detection got us down to three tests
We’re left with three tests for this gate if we’re interested in fault detection.
If we’re interested in fault location, we need more
To isolate y s-a-1
Need to apply both 10 and 01
10, alone, detects the equivalent faults y s-a-1 and z s-a-0
01, alone, detects the equivalent faults x s-a-1 and z s-a-0
Together, they can isolate the three faults (assuming only one fault active). Tg Tf 10 01 00 x
sa1 z
sa0
sa1 y
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VLSI Design II: VHDL

32. Overall process define fault model set of faults for circuit
select target fault
no more faults: done
generate test for target
fault simulate
discard detected faults
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VLSI Design II: VHDL

33. Test Generation Toward an algorithmic means to generate test vectors
What do we want in a test vector?
fault activation and propagation
if the discrepancy D wiggles (i.e. from good to bad), then so does the output
how do we determine if a function changes with respect to a variable
Use Automatic Test Generation algorithms (ATG)
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VLSI Design II: VHDL

34. Primary inputs and outputs
Test generation algorithms work in terms of:
Primary inputs — (PI) a controllable input to a circuit. E.g. A pin on an IC, or an output of an FF in a scan system
Primary outputs — (PO) an observable output of the circuit. E.g. A pin on an IC, or a D input to an FF in a scan system
They all operate in terms of:
finding the appropriate PIs to control to activate a fault
finding the appropriate PIs to control to propagate a discrepancy to one of the POs.
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VLSI Design II: VHDL

35. Propagate, Justify A few definitions
justify, justification — the process of selecting PIs to force a certain line to have a specific value
the verb … justify a 0 on the input a of gate B
the noun … justification is the process of justifying
propagate, propagation — the process of selecting appropriate PIs that allow a discrepancy “D” to be pushed to a PO
… propagate the D to any output
… propagation is the process
involves justification a PO
PIs B
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VLSI Design II: VHDL

36. Imply all you can… Forward implication
Def: Knowing one or more gate inputs, imply the output value.
Assume all gate inputs are the same value — either all c or all c’
Then the output is
output = value  i
We can refine this if we know the controlling value
i.e. only one of the inputs needs to have c to know output
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VLSI Design II: VHDL

37. Look behind yourself too…
Backward implication
Def: Knowing the output and possibly some inputs, imply one or more of the inputs
Assume all gate inputs are the same — either all c or c’
Then the inputs are:
inputs = output  i
We can refine this if we know the controlling value
If the input needed to produce the output is c, then only one input needs to have it.
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VLSI Design II: VHDL

38. Justify Algorithm
Justify (l , v) — Recursive algorithm to justify line l to value v
l = v
if l is a primary input return — you’re done on this path
set c and i to controlling/inversion values of gate driving l
inval = v  i
if (inval == c)
select one input j of gate l
Justify (j, inval)
else
for every input j of gate l l 1 x
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VLSI Design II: VHDL

39. An example of justification
l = v
if l is a primary input return — you’re done on this path
set c and i to controlling/inversion values of gate driving l
inval = v  i
if (inval == c)
select one input j of gate l
Justify (j, inval)
else
for every input j of gate l
justify a to 1 a PO B
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VLSI Design II: VHDL

40. Test Generation: Propagate Algorithm
Prop (l , err) — Propagate value err from line l
l = err
if line l is a primary output return — you’re home
k = fanout gate of line l
c,i = controlling/inversion value of gate k
for every input j of k other than l
Justify (j, c’)
Propagate (k, err  i) l k
Justify enabling values onto other inputs
Propagate
further
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VLSI Design II: VHDL

41. Will this always work? Will justify and propagate always work?
Circuits without reconvergent fanout
“select one” and “justify” are each independent of any previous justification
you’re guaranteed that propagation and justify will not interfere x1 x2 x3 x4 Z x5
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VLSI Design II: VHDL

42. Test Generation: Basic Algorithm
Algorithm to test line l s-a-v
begin
set all values to x (unknown)
Justify line l to value v’
if (v == 0)
Propagate D on line l
else Propagate D’ on line l
end
Will require more justification x1 x2 x3 x4 Z x5
s-a-0
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VLSI Design II: VHDL

43. Automatic Test-Pattern Generation (ATPG)
Test U2.ZN for s-a-1
1) Activate (excite) fault => U2.ZN = 0
2) Work backward => A = 0
3) Work forward (sensitize the path to PO) => U3.A2 = 1, U5.A2 = 1
4) Work backward (justify outputs) => ABC = 110
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VLSI Design II: VHDL

44. Reconvergent Fanout Fault U4.A1 s-a-1? Fault B s-a-1?
Signal B branches and then reconverges at logic gate U5.
ATPG works.
We create two sensitized paths that prevent fault from propagating to the PO.
The problem can be solved by changing A to 0, but this breaks rules of the ATPG!
The PODEM algorithm solves the problem.
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VLSI Design II: VHDL

45. Test Generation — example
With reconvergent fanout
Fanout paths from a gate reconverge at some later gate
Inputs needed for propagation may be inconsistent with ones needed for justification G2 G4 G5 a b c d e
s-a-1 D’ G3 G1
Procedure:
justify G1 to 0 —> a=b=c=1
propagate to G4 —>
requires G2 = 1
but a=1 makes G2=0
Inconsistency — crash and burn
Kaboom!
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VLSI Design II: VHDL

46. Test generation — example, cont’d
Need to backtrack — propagate on other path
backtrack
Procedure:
justify G1 to 0 —> a=b=c=1
propagate to G4 —>
requires G2 = 1
but a=1 makes G2=0
Inconsistency
propagate to G5 —>
justify G3 to 1
this works with e=0 G2 G4 G5 a b c d e
s-a-1 D’ G3 G1
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VLSI Design II: VHDL

47. Backtracking Backtracking requires that a decision tree be maintained
Each node describes a design’s state
values previously justified on lines
implications, forward and backward
Each arc describes a new decision
justify a line, activate a fault
Need to be able to go back…
to former state
State 1
State 1A
State 1A1
State 1A2
State 1B
fail
win
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VLSI Design II: VHDL

48. Maintaining the decision tree
Procedure:
justify G1 to 0 —> a=b=c=1
propagate to G4 —>
requires G2 = 1
but a=1 makes G2=0
Inconsistency
propagate to G5 —>
justify G3 to 1
this works with e=0
State 1 all x’s
backtrack
justify G1 to 0
a=b=c=1
State 1A
Prop. to G4
Prop. to G5
G2=1, a=1
inconsistency
fail
G3 = 1
e = 0
win
State 1A1
State 1A2
Backtrack, G2=1 no longer part of design state. Revert to previous state.
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VLSI Design II: VHDL

49. Observations on approach
Enumeration used
justify algorithm was recursive
When gate has controlling value on input, one path selected
may need to backtrack and follow another
eventually, may need to follow all
Propagate algorithm was recursive
When there is a fanout at a propagation point, one path selected toward output
The backtracking, again, is due to reconvergent fanouts and previous values justified on them
No solution? — redundant wrt the fault
As it turns out…
The natural state maintenance in recursive programs can keep track of the decision tree
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VLSI Design II: VHDL

50. More terminology When propagating a discrepancy D - frontier
Often, due to fanout, there are several options
Propagate needs to pick one for the sensitized path
D - frontier
The D-frontier is the set of all gates with D or D’ on one or more inputs and an x on its output (no other inputs are controlling)
This is the set from which you select a propagation (sensitization) path D’ x
D-frontier
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VLSI Design II: VHDL

51. D-Frontier Back to our example d G2 G4 a s-a-1 D’ b G1
After the activation of the fault, and forward implication, the D- frontier is … ?
If D-frontier = Ø, then no path to primary output
failure, backtrack
previous justifications have made this path impossible G3 1 x G2 G4 G5 a b c d e
s-a-1 D’ G1
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VLSI Design II: VHDL

52. J-Frontier In line justification…
The J-frontier is the set of all gates whose output values are known, but the outputs are not implied (yet) by the inputs
Some inputs may be known, but the current output value is not implied
Similar to D-frontier, but looking backward 1
J-frontier x
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VLSI Design II: VHDL

53. J-Frontier Back to the Example
The fault is activated and forward implication is done
A gate is selected from the D-frontier for propagation
In this case, G5 is the only choice
The J-frontier is then … ? G3 1 x G2 G4 G5 a b c d e
s-a-1 D’ G1
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VLSI Design II: VHDL

54. Implication Revisited
Implication Process
Compute all values uniquely determined by implication
1, 0, D, D’, x — looking forward and backward
more aggressive than previous implication
maintain the D and J frontier
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VLSI Design II: VHDL

55. Backward Implication new implication front implication front After
Before x
<— 1
<—1 1 x
<— 1 x
<—0
<— 1 1 x
<—0 x
J-frontier = {…}
J-frontier = {… , a} x a a x
<—1 1 x
<— 1 1 x
<— 1
1 —>
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VLSI Design II: VHDL

56. Forward Implication After Before 0—> 0—> x x x 1—> 1 1—> x
0—> x x x
1—> 1
1—> x 1 1
0—> a a
J-front={…, a}
J-front={…} x x
1—> a a 1
J-front={…}
J-front={…, a}
<—0 x D x a D
D—> a
D-front={…, a}
D-front={…}
1—> 1 D x a D
D-front={…, a}
0—>
D-front={…}
0—>
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VLSI Design II: VHDL

57. Where are we now? Pieces of test generation algorithms seen To come
justify, propagate
problems with reconvergent fanout
need to backtrack — makes for a messier algorithm
need to keep track of state, and what combinations have been tried before.
heuristics to guess at best “next path” to follow
To come
D algorithm
and eventually Podem
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VLSI Design II: VHDL

58. Implication Process Revisited
Unique D-drive
If there is only one gate on the D frontier, then implication propagates D through the gate.
It’s the only direction D could propagate
before
after D D x
D’ —> a x
<— 1
D-frontier = {a}
D-frontier = { }
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VLSI Design II: VHDL

59. All Pieces in Place Pieces Discussion of the D algorithm
Controlling and inverting values
Fault activation
Justification
Propagation
Forward/backward implication
D and J frontiers
Decision tree maintenance
Discussion of the D algorithm
note that this is a version of the D algorithm
a number of situations have been left open, e.g.
“select an input …”, “select a gate …”
which one?
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VLSI Design II: VHDL

60. D-Algorithm Initialization 1. Propagate D to PO 2. Justify all values
set all line values to X
activate the target fault by assigning logic value to that line
1. Propagate D to PO
2. Justify all values
Imply_and_check() does only necessary implications, no choices
if D-alg() == SUCCESS then return SUCCESS
else undo assignments and its implications
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VLSI Design II: VHDL

61. Test Generation: The D Algorithm
Decorate design with all known values. Check for inconsistencies.
if (imply_and_check() == FAIL) return FAIL
if (error not at primary output) {
if (D-frontier == Ø) return FAIL
repeat {
select an untried gate (G) from D-frontier
c = controlling value of G
assign c’ to every input of G with value x
if (D-Alg() == SUCCESS) return SUCCESS
} until all gates from D-frontier tried
return FAIL}
if (J-frontier == Ø) return SUCCESS
select a gate G from the J-frontier
select an input (j) of G with value x, assign c to j
assign c’ to j /* reverse decision*/
} until all inputs of G are specified
return FAIL
Push D to a primary output
Once at primary output, justify all values needed to have D on the primary output
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VLSI Design II: VHDL

62. A circuit and fault to testb c d e f g h i j k l m n d’ e’ f’
s-a-1
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VLSI Design II: VHDL

63. Tracing through an example1 a b d e f g h i j k l m n d’ e’ f’
s-a-1
all x’s
a = 0, b = c = 1 D 1 1
Decisions Implications Comments
a = 0 Activate the fault
h = 1
b = 1 Unique D-drive through g
c = 1 (the unique path for D)
g = D D-frontier becomes {i,k,m}
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VLSI Design II: VHDL

64. Tracing through an example1 a b d e f g h i j k l m n d’ e’ f’
s-a-1
all x’s 1 D’
a = 0, b = c = 1 D 1 1
d = 1
Decisions Implications Comments
d=1 Propagate through i
i = D’
d’ = 0 D-frontier becomes {k, m, n}
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VLSI Design II: VHDL

65. Tracing through an example1
all x’s a b d e f g h i j k l m n d’ e’ f’
s-a-1 1 D’ 1
a = 0, b = c = 1 D D 1 1 1 1
d = 1 1 1
j=k=l=m=1
Bang
Decisions Implications Comments
j=k=1 Propagate through n
l=m=1
n=D
e’=0, e=1
k=D’ But k = 1 Contradiction!
D-frontier remains {k, m, n}
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VLSI Design II: VHDL

66. Tracing through an example
all x’s 1 a b d e f g h i j k l m n d’ e’ f’
s-a-1 1 D’
a = 0, b = c = 1 1 D 1 D’ 1
d = 1 1
e = 1
j=k=l=m=1
Bang
Decisions Implications Comments
e = 1 Propagate through k
k=D’
e’=0
j=1 D-frontier becomes {m, n}
13/01/2019
VLSI Design II: VHDL

67. Tracing through an example
all x’s 1 a b d e f g h i j k l m n d’ e’ f’
s-a-1 1 D’
a = 0, b = c = 1 1 D 1 D’
d = 1 1 1 1 1 1
e = 1
j=k=l=m=1
Bang
Decisions Implications Comments
l=m=1 propagate through n
n = D
f’= 0
f = 1
m = D’ But m = 1, contradiction!
D-frontier remains {m, n}
l=m=1
Bang
13/01/2019
VLSI Design II: VHDL

68. Tracing through an example
all x’s 1 a b d e f g h i j k l m n d’ e’ f’
s-a-1 1 D’
a = 0, b = c = 1 1 D D 1 D’
d = 1 1 1 1 1 D’
e = 1
j=k=l=m=1
Bang
Decisions Implications Comments
f = 1 Propagate through m
m = D’
f’ = 0
l = 1
n = D J-frontier is Null
l=m=1
Bang
f = 1, n = D
party!
13/01/2019
VLSI Design II: VHDL

69. What about the J-frontier?
In this example, all inputs were easily justified through implication
essentially, d, e, and f were primary inputs
if these were driven by other gates, the earlier inputs might not have been implied. e.g. x a a x
<— 0 x x
J-frontier = {…}
J-frontier = {…, a}
13/01/2019
VLSI Design II: VHDL

70. What about the J-frontier?
The D-algorithm:
picks a gate from the J-frontier
and then tries to set each input to a controlling value
If that value fails due to imply_and_check, it is inverted and a new input is tried
how does it handle the case where none of the inputs should be controlling?
if (J-frontier == Ø) return SUCCESS
select a gate G from the J-frontier
c = controlling value of G
repeat {
select an input (j) of G with value x, assign c to j
if (D-Alg() == SUCCESS) return SUCCESS
assign c’ to j /* reverse decision*/
} until all inputs of G are specified
return FAIL
exit here if output of gate G is justified, possibly before setting all inputs
13/01/2019
VLSI Design II: VHDL

71. J-Frontier Assume a change to the example circuit
Then we would be left with elements in the J-frontier set
J-frontier is {f}
If the x’s are primary inputs, this is easy
If they’re not primary inputs,
more gates begin to show up in J-frontier
you may not be able to set the input you select to the controlling value
If there is a redundancy, the whole process might fail. 1 a b d e f g h i j k l m n d’ e’ f’
s-a-1 x 1 D’ 1 D D 1 D’ 1 1 1 x 1 D’
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VLSI Design II: VHDL

72. Another example all x’s j a Decision Tree g b k c c-sa0 f d i e h
decisions implications comments
13/01/2019
VLSI Design II: VHDL

73. Another example all x’s c=1, b=1 j a Decision Tree D’ g h=1 1 b k 1 cf g h i j k
Decision Tree D’
h=1 1 1
c-sa0 D D’ D
j=0
a=1 1
d=0
decisions implications comments
c=1,b=1,g=f=D’
activate fault, unique D drive
h=1 i=D prop through i. j,k=Df; h=Jf
a=1 j=D’, k=1 prop through j. Df = null. backtrack
(a = x)
j=0 a=0, k=D prop through i, fault at output
d=0 justify h
13/01/2019
VLSI Design II: VHDL

74. Summary: D algorithm How does it work … Conceptually When propagating
Activate fault and propagate
Then justify the remaining gates
When propagating
assign c’ to other inputs of the gates on the sensitized path
do forward and backward implication
when going backward, specify gate inputs if they are all c’
if one input should be c, put gate into J-frontier 1
s-a-1 x a
<— 1 1
13/01/2019
VLSI Design II: VHDL

75. Summary: D algorithm Oh, by the way… justify the rest of these inputs
That is, the D-frontier is pursued with only partial regard to whether the c’ values selected are self consistent
In the process, the J-frontier grew large
5 gates shown highlighted
plus the gates that drive them
… and there’s lots of reconvergent fanout to cause justification problems. 1
s-a-1
circuit messed up to make a point
13/01/2019
VLSI Design II: VHDL

76. Summary: D Algorithm Depth-first push toward primary output
do justification and consistency afterward as needed
backward implication can cause problems
use backtracking as necessary
Exhaustive, exponential
The number of operations performed is an exponential function of the number of gates
This is worst case, typically only seen when a fault turns out to be undetectable
But you don’t know it’s undetectable until you exhaustively try everything
Heuristics for “selecting one of …” help reduce search time of successful searches
Test generators are often limited in their search depth, thus some detectable faults don’t have tests.
13/01/2019
VLSI Design II: VHDL