1. Day 21: October 29, 2010 Registers Dynamic Logic
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems
Day 21: October 29, 2010
Registers
Dynamic Logic
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2. Today Clocking Dynamic Logic Registers Timing discipline
Dynamic Registers
Dynamic Logic
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3. Register Passhold on input latch samples value
Holdpass on output latch presents stored value to circuit
Master and Slave latches
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4. Register How long from f1 fall to output?
At least part of clkoutput (tclk-q)
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5. Clock Signal Can we use a single signal for clock?
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6. Clock Issues Possible failure modes? Flow through during transition?
Loading on clock phases
Delay in compute f1?
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7. Appropriate Delay Creates non-overlap
Feed thru
here also
Bad.
Appropriate Delay
Creates non-overlap
Too much could allow flow through
Text page 339
example generation
non-overlapping clocks.
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8. Clocking Discipline
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9. Clocking Discipline
Follow discipline of combinational logic broken by registers
Compute
From state elements
Through combinational logic
To new values for state elements
As long as clock cycle long enough,
Will get correct behavior
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10. Gate-Latch-Register Transistor Count? Total Transistor Width?
Capacitive load on data input?
Capacitive load on clock?
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11. Alternate Registers
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12. How does this work as a register?
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13. Compare Gate-Latch-Register
Transistor Count?
Total Transistor Width?
Load on input?
Load on Clock(s)?
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14. Weaknesses?
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15. Weaknesses Hold value on capacitance Not drive to rail
Not actively driven
Easily upset by noise
Will leak away eventually
Sets lower bound on clock frequency
Cannot “gate off” clock when not in use
Not drive to rail
Less noise margin
More static leakage – PMOS not completely off
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16. How Improve?
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17. Transmission Gate Register
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18. Level Restore
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19. CCMOS
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20. Make Static Maybe reduce capacitance by
swapping order of feedback and phi
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21. Make Static Transistors? Total width? Clock load? Input load?
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22. Class Ended Here
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23. Dynamic Logic

24. Motivation Still like to avoid driving pullup/pulldown networks
reduce capacitive load
Power, delay
Ratioed had problems with
Large device for ratioing
Slow pullup
Static power

25. Idea
Use clock to disable pullup during evaluation

26. Advantages Large device Single network Driven by clock not data/logic
Can pullup quickly w/out putting load on logic
Single network
pulldown

27. Domino Logic

28. Domino Everything charged high After inverter all inputs low
Disabled, waiting for an enabling transition
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29. Domino or4

30. Domino Logic How fast can we evaluate? Compare to CMOS case?
R0/2 input
Compare to CMOS case?

31. Requirements Single transition All inputs at 1 during precharge
Precharge to 0 so inversion makes 1
Non-inverting gates
Fires only once

32. Issues
Noise sensitive
Power?
Activity?

33. Admin Homework 5 Normal lectures next week
Changed due date to Friday, Nov. 5th
Normal lectures next week
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34. Ideas Clocked circuit discipline Pass-gate based register efficiency
Uses state holding element
Prevents
Combinational loops
Timing assumptions
(More) complex reasoning about all possible timings
Pass-gate based register efficiency
Dynamic/clocked logic
Faster than CMOS, more noise prone
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