1. The University of Adelaide, School of Computer Science
14 January 2019
Lecture 2.5
Instructions: Branch and Jump Instructions
Chapter 2 — Instructions: Language of the Computer

2. Learning Objectives
Understand that instruction label cannot be presented in binary representation directly
Understand that the offset (in branch) and the address (in jump) have the unit of word
Use the address of the next instruction as the base address
Covert branch and jump instructions between assembly statements and binary representations
Use slt instruction with beq/bne to implement more complicated branch conditions
Chapter 2 — Instructions: Language of the Computer — 2

3. Coverage Textbook Chapter 2.7
Chapter 2 — Instructions: Language of the Computer — 3

4. Control Flow Instructions
The University of Adelaide, School of Computer Science
14 January 2019
Control Flow Instructions
Branch to a labeled instruction if a condition is true
Otherwise, continue sequentially
beq $rs, $rt, L1
if (rs == rt) branch to instruction labeled L1;
bne $rs, $rt, L1
if (rs != rt) branch to instruction labeled L1;
Instruction Format (I format)
§2.7 Instructions for Making Decisions op rs rt
Offset
6 bits
5 bits
16 bits
Chapter 2 — Instructions: Language of the Computer — 4
Chapter 2 — Instructions: Language of the Computer

5. Compiling If Statements
The University of Adelaide, School of Computer Science
14 January 2019
Compiling If Statements
C code:
if (i==j) f = g+h; else f = g-h;
f,g,h,i,j in $s0,$s1,$s2,$s3,$s4
Compiled MIPS code:
bne $s3, $s4, Else add $s0, $s1, $s j Exit Else: sub $s0, $s1, $s2 Exit: …
Assembler calculates addresses
Chapter 2 — Instructions: Language of the Computer — 5
Chapter 2 — Instructions: Language of the Computer

6. Compiling If Statements
The University of Adelaide, School of Computer Science
14 January 2019
Compiling If Statements
C code:
if (i==j) f = g+h; else f = g-h;
f,g,h,i,j in $s0,$s1,$s2,$s3,$s4
Compiled MIPS code:
beq $s3, $s4, If sub $s0, $s1, $s j Exit If: add $s0, $s1, $s2 Exit: …
Assembler calculates addresses
Chapter 2 — Instructions: Language of the Computer — 6
Chapter 2 — Instructions: Language of the Computer

7. Control Flow Instructions
The University of Adelaide, School of Computer Science
14 January 2019
Control Flow Instructions
Branch to a labeled instruction if a condition is true
Otherwise, continue sequentially
beq $rs, $rt, L1
bne $rs, $rt, L1
Instruction Format (I format)
How to specify the branch destination address?
§2.7 Instructions for Making Decisions op rs rt
Offset
6 bits
5 bits
16 bits
Chapter 2 — Instructions: Language of the Computer — 7
Chapter 2 — Instructions: Language of the Computer

8. Specifying Branch Destinations
Use a base address (like in lw) added to the 16-bit offset
Which register? Instruction Address Register (Program Counter)
Its use is automatically implied by instructions
PC gets updated (PC+4) during the fetch stage so that it holds the address of the next instruction
Instruction address is always the multiple of 4. The unit of the offset is word
Limit the branch distance to -215to (word) instructions from the instruction after the branch instruction
Chapter 2 — Instructions: Language of the Computer — 8

9. Calculate Branch Destination Address
Target address = Base address + Offset × 4
Offset = (Target address – Base address) / 4
= Address difference / 4
Target address: the address of the labelled instruction
Base address: the address of the instruction following the branch instruction
Chapter 2 — Instructions: Language of the Computer — 9

10. Compiling Loop Statements
The University of Adelaide, School of Computer Science
14 January 2019
Compiling Loop Statements
C code:
while (save[i] == k) i += 1;
i in $s3, k in $s5, address of save[] in $s6
All items in save[] are 32-bit words
Compiled MIPS code:
Loop: sll $t1, $s3, add $t1, $t1, $s lw $t0, 0($t1) bne $t0, $s5, Exit addi $s3, $s3, j Loop Exit: …
Chapter 2 — Instructions: Language of the Computer — 10
Chapter 2 — Instructions: Language of the Computer

11. Branch Instruction Design
The University of Adelaide, School of Computer Science
14 January 2019
Branch Instruction Design
Why not blt, bge, etc?
Hardware for <, ≥, … slower than =, ≠
Combining comparisons such as “<” with branch involves more work for a branch instruction, requiring a slower clock
All instructions are penalized!
beq and bne are the common and fast cases
This is a good design compromise
Chapter 2 — Instructions: Language of the Computer — 11
Chapter 2 — Instructions: Language of the Computer

12. In Support of Branch Instructions
We have beq, bne, but what about other kinds of branches (e.g., branch-if-less-than)?
Set on less than instruction:
slt $rd, $rs, $rt
if (rs < rt) rd = 1; else rd = 0;
Instruction format: R format
Alternate versions of slt
sltu $rd, $rs, $rt
slti $rt, $rs, Imm # SignExt
sltiu $rt, $rs, Imm # SignExt
Chapter 2 — Instructions: Language of the Computer — 12

13. The University of Adelaide, School of Computer Science
14 January 2019
Signed vs. Unsigned
Signed comparison: slt, slti
Unsigned comparison: sltu, sltui
Example
$s0 =
$s1 =
slt $t0, $s0, $s1 # signed
–1 < +1  $t0 = 1
sltu $t0, $s0, $s1 # unsigned
+4,294,967,295 > +1  $t0 = 0
Chapter 2 — Instructions: Language of the Computer — 13
Chapter 2 — Instructions: Language of the Computer

14. Pseudo Branch Instructions
Can use slt, beq, bne, and the register $zero to create other conditions
less than blt $s1, $s2, Label
less than or equal to ble $s1, $s2, Label
greater than bgt $s1, $s2, Label
greater than or equal to bge $s1, $s2, Label
Such branches are included in the instruction set as pseudo instructions - recognized and expanded by the assembler
Assembler needs a reserved register ($at)
slt $at, $s1, $s2 #$at set to 1 if
bne $at, $zero, Label #$s1 < $s2
Chapter 2 — Instructions: Language of the Computer — 14

15. The University of Adelaide, School of Computer Science
14 January 2019
Unconditional Jump
Jump (j) targets could be anywhere in text segment within 256 (i.e., 228) MB
Encode full address in instruction
Instruction format: J format op
address
6 bits
26 bits
(Pseudo)Direct jump addressing
Target address = (PC+4)31…28:(address×4)
address×4 = (Target address)27…0
PC is the address of the jump instruction
Chapter 2 — Instructions: Language of the Computer — 15
Chapter 2 — Instructions: Language of the Computer

16. Form the target address
PC+4 4 32 26 00
from the low order 26 bits of the jump instruction
Where the 4 bits come from?
The upper 4 bits of the address of the instruction following the Jump instruction
Chapter 2 — Instructions: Language of the Computer — 16

17. Target Addressing Example
The University of Adelaide, School of Computer Science
14 January 2019
Target Addressing Example
Loop code from earlier example
Assume Loop at location 80000
Loop: sll $t1, $s3, 2
80000 19 9 2
add $t1, $t1, $s6
80004 22 32
lw $t0, 0($t1)
80008 35 8
bne $t0, $s5, Exit
80012 5 21
addi $s3, $s3, 1
80016 1
j Loop
80020
Exit: …
80024
Chapter 2 — Instructions: Language of the Computer — 17
Chapter 2 — Instructions: Language of the Computer

18. Target Addressing Example
The University of Adelaide, School of Computer Science
14 January 2019
Target Addressing Example
Loop code from earlier example
Assume Loop at location 80000
Loop: sll $t1, $s3, 2
80000 19 9 2
add $t1, $t1, $s6
80004 22 32
lw $t0, 0($t1)
80008 35 8
bne $t0, $s5, Exit
80012 5 21
addi $s3, $s3, 1
80016 1
j Loop
80020
20000
Exit: …
80024
Chapter 2 — Instructions: Language of the Computer — 18
Chapter 2 — Instructions: Language of the Computer

19. The University of Adelaide, School of Computer Science
14 January 2019
Branching Far Away
If branch target is too far to encode with 16-bit offset, assembler rewrites the code
Example
beq $s0,$s1, L1
L2: … ↓
bne $s0,$s1, L2 j L1 L2: …
Chapter 2 — Instructions: Language of the Computer — 19
Chapter 2 — Instructions: Language of the Computer