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Presentation Title Greg Snider QSR, HP Laboratories
Nano Architectures I Greg Snider QSR, HP Laboratories
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Personal Introduction
Presentation Title Background: Analog circuit design Logic design, synthesis Control Communications Operating systems Network protocols Digital signal processing Compilers Medical instrumentation Simulation User interfaces E-commerce Currently (HP Labs): Nano architectures, circuits, compilation, simulation January 14, 2019
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Personal Introduction
Presentation Title Background: Analog circuit design Logic design, synthesis Control Communications Operating systems Network protocols Digital signal processing Compilers Medical instrumentation Simulation User interfaces E-commerce Currently (HP Labs): Nano architectures, circuits, compilation, simulation Nano interdisciplinary January 14, 2019
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Goal: NanoProcessor Problems of the nano-scale: Assembly limitations
Defects (permanent errors) Faults (thermal, subatomic particles, …) Interfacing (configuration, I/O) January 14, 2019
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Goal: NanoProcessor What is the architectural response?
Problems of the nano-scale: Assembly limitations Defects (permanent errors) Faults (thermal, subatomic particles, …) Interfacing (configuration, I/O) What is the architectural response? January 14, 2019
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What I’ll show you TODAY: Nano architecture at HP Labs Bottom up tour:
Building blocks (tiles, mosaics) Brief FET / logic tutorial 5 nano logic families (1 weird one) Architectures and idioms Compilation and simulation DEMO: design environment January 14, 2019
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What I’ll show you FRIDAY: Living in an imperfect world
Transient faults History (von Neumann) Approaches (coding theory) Static defects Background (Teramac) Empirical studies DEMO: 4-bit nanoprocessor January 14, 2019
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Building Blocks: Tile Crossbar January 14, 2019
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Building Blocks: Tile interlayer January 14, 2019
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Building Blocks: Tile Crossbar junction January 14, 2019
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Configuring a junction
+ V junction - V January 14, 2019
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Configurable Tile January 14, 2019
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Tile Types January 14, 2019
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Mosaics January 14, 2019
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Nanowires / microwires
junction January 14, 2019
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Interfacing: one scenario
silicon substrate Substrate provides through microwires: power clock data I/O configuration I/O January 14, 2019
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Field Effect Transistor (FET) tutorial
INPUT A controllable switch N-FET January 14, 2019
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Field Effect Transistor (FET) tutorial
N-FET January 14, 2019
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Field Effect Transistor (FET) tutorial
N-FET January 14, 2019
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Field Effect Transistor (FET) tutorial
1 1 N-FET January 14, 2019
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Field Effect Transistor (FET) tutorial
1 1 N-FET January 14, 2019
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Field Effect Transistor (FET) tutorial
1 1 N-FET January 14, 2019
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Field Effect Transistor (FET) tutorial
1 1 N-FET January 14, 2019
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Field Effect Transistor (FET) tutorial
INPUT P-FET January 14, 2019
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Field Effect Transistor (FET) tutorial
1 P-FET January 14, 2019
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Field Effect Transistor (FET) tutorial
1 1 P-FET January 14, 2019
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Field Effect Transistor (FET) tutorial
P-FET January 14, 2019
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Field Effect Transistor (FET) tutorial
P-FET January 14, 2019
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Field Effect Transistor (FET) tutorial
P-FET January 14, 2019
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Field Effect Transistor (FET) tutorial
P-FET January 14, 2019
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Field Effect Transistor (FET) tutorial
P-FET January 14, 2019
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FET Summary 1 N-FET P-FET Closed switches January 14, 2019
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Logic Tutorial Inverter January 14, 2019
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Logic Tutorial Inverter 1 January 14, 2019
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Logic Tutorial Inverter 1 January 14, 2019
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Logic Tutorial Inverter January 14, 2019
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Logic Tutorial Inverter January 14, 2019
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Logic Tutorial Inverter 1 January 14, 2019
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Logic Tutorial 1 0 = false = LO 1 = true = HI Inverter
1 0 = false = LO 1 = true = HI January 14, 2019
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Logic Tutorial Inverter FET / Resistor Logic + V January 14, 2019
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Logic Tutorial Inverter FET / Resistor Logic + V 1 January 14, 2019
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Logic Tutorial Inverter FET / Resistor Logic + V 1 January 14, 2019
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Logic Tutorial Inverter FET / Resistor Logic + V 1 January 14, 2019
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Logic Tutorial Inverter FET / Resistor Logic + V 1 January 14, 2019
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Logic Tutorial Inverter CMOS Logic + V January 14, 2019
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Logic Tutorial Inverter CMOS Logic + V 1 January 14, 2019
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Logic Tutorial Inverter CMOS Logic + V 1 January 14, 2019
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Logic Tutorial NAND (not AND) gate January 14, 2019
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Logic Tutorial NAND (not AND) gate 1 January 14, 2019
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Logic Tutorial NAND (not AND) gate 1 1 January 14, 2019
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Logic Tutorial NAND (not AND) gate 1 1 January 14, 2019
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Logic Tutorial NAND (not AND) gate 1 1 January 14, 2019
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Logic Tutorial + V NAND January 14, 2019
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Logic Tutorial + V + V NAND January 14, 2019
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Logic Tutorial AND-OR-INVERT January 14, 2019
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Logic Tutorial What a mess! AND-OR-INVERT Can we implement in mosaics?
January 14, 2019
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Mosaic Logic n-FET / resistor logic p-FET / resistor logic
n-FET / p-FET logic Diode / resistor logic Hysteretic / resistor logic January 14, 2019
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1. n-FET / resistor logic GND A A B B C C AB + C V+ January 14, 2019
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2. p-FET / resistor logic V+ A A B B C C AB + C GND January 14, 2019
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3. n-FET / p-FET logic configurable p-FETs configurable n-FETs
+ V Ground configurable p-FETs configurable n-FETs configurable switches January 14, 2019
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3. n-FET / p-FET logic + V Ground January 14, 2019
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3. n-FET / p-FET logic + V Ground January 14, 2019
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4. Diode / resistor Logic + + + + A A B B C C AB + AC January 14, 2019
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5. Hysteretic Resistor logic
January 14, 2019
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Hysteretic Resistors -V January 14, 2019
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Hysteretic Resistors -V January 14, 2019
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Hysteretic Resistors -V January 14, 2019
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Hysteretic Resistors January 14, 2019
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Hysteretic Resistors +V January 14, 2019
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Hysteretic Resistors +V January 14, 2019
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Hysteretic Resistors +V January 14, 2019
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Hysteretic Resistors 1 Bit Latch open = logic 1 closed = logic 0
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Hysteretic Resistors 1 Bit Latch Vswitch ≈ 1.5 V Vdestroy ≈ 2.5 V
Open/Closed resistance varies. Vswitch varies. 1 Bit Latch open = logic 1 closed = logic 0 January 14, 2019
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Latch Arrays A B C D E January 14, 2019
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Latch Arrays Input and Output shared ?!!? Can you do logic with these?
B C D E January 14, 2019
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YES ! Latch Arrays Input and Output shared ?!!?
Can you do logic with these? A B C D E YES ! January 14, 2019
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Hysteretic resistor logic schema
clocks A A minterm input latches A A B B B B NOR + output latches f (A, B) Crossbar g (A, B) January 14, 2019
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Hysteretic resistor crossbar
January 14, 2019
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Hysteretic resistor crossbar
Destroyed junctions (“stuck open”) Working junctions January 14, 2019
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NAND gate (1) All latches opened (2) Input data latched
B 1 C (1) All latches opened (2) Input data latched (3) Wired-AND junctions closed 1 (4) Wired-AND computed, latched (5) Wired-AND junctions opened (6) Result driven out January 14, 2019
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Architecture Logic Blocks Composite structures Hierarchies Folding
January 14, 2019
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Logic Blocks A B C input section output section January 14, 2019
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Antisymmetric Array crossbar input section output section
January 14, 2019
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Signal Flow Rent’s Rule: connections tend to be local!
January 14, 2019
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Antisymmetric Array: 2-Bit Incrementer
A B A’ B’ AB + BA B A GND V+ January 14, 2019
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Bidirectional Buffer GND V+ January 14, 2019
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Hierarchies Routing Bidirectional Buffers Logic Fabrics
January 14, 2019
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Folded Arrays January 14, 2019
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Multi-folded Arrays (c) January 14, 2019
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Getting rid of tiles? January 14, 2019
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Getting rid of tiles? p-FETs n-FETs Might have same interlayer!
January 14, 2019
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Getting rid of tiles? fold January 14, 2019
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Getting rid of tiles? Folding: Eliminates tiles More layers fold
P semiconductor nanowires Metal nanowires (gates) N semiconductor nanowires Metal nanowires (switches) Transistor Interlayer fold Switch Interlayer Folding: Eliminates tiles More layers January 14, 2019
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Key Points Tile = crossbar with configurable junctions
Mosaic = set of tiles logic Hierarchy of mosaics system Folding: tiles layers January 14, 2019
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