1. CS/COE 0447 Jarrett Billingsley
CPU Intro
CS/COE 0447
Jarrett Billingsley

2. Class announcements OMETs are up!!!
≥70% completion == homemade cookies for the final
so do them!
CS447

3. Parts of the CPU
CS447

4. We have all the pieces now…
we've learned about how hardware can… Y A B S
do any kind of boolean logic… +
make decisions…
do math…
LET'S MAKE A CPU!!!
and do multi-step procedures.
remember things… D Q en D Q
state register
transition logic
inputs
output logic
outputs
- hardware and software have equal computational capability.
- anything you can do in one, you can do in the other.
- isn't turing completeness neat?
CS447

5. Remember this? + unresolved questions: what's the control?
what's the datapath?
how does it know what instruction to get next?
how does it know which registers to access?
how does it know whether it should add, subtract, etc.?
Control
Registers
Datapath
Processor
Memory
Program 3 5 8
instruction A B C +
CS447

6. ÷ + × - ⊕ ☃ ∫ & Zooming in fp t0 s4 at sp eax?
there are a few major parts of any CPU:
hi i'm memory!!
Control
the control tells everything else what to do, and when
if(add)
do this
else if...
Registers
Datapath ÷ fp + t0 × s4 - at ⊕
control signals! ∫ ☃
& sp
eax?
values move between them
registers hold the values being computed
the datapath computes new values
- what, you've never seen the snowman operator?
CS447

7. OKAY, MEMORY, WHAT DO YOU WANT??
registers are just a temporary stopping point for your program's data
you could have a computer with few/no registers at all!
Control
Datapath
Memory
this is a memory-memory machine
if you squint and wave your hands really hard, every computer is.
the registers and the memory only differ in their speed and size.
- really, we only have registers because our memory technologies are imperfect and we have to play to the strengths of each.
- if we suddenly had a breakthrough in memory technology, we could unify the registers, memory, and persistent storage and be done with it.
CS447

8. ISA and hardware design
CS447

9. Remember what an ISA is?
it's the software interface the programmer uses to control the CPU
what are some important aspects of the MIPS ISA?
what instructions does it have?
how many registers does it have?
how are they encoded into binary?
how big are they?
are there any special registers?
how many operands do they have?
how does it access memory?
the ISA abstracts the hardware design (the microarchitecture)
- Instruction Set Architecture
- it has bit registers, plus 3 more…
- $zero is always 0, and ra is used by jal, but otherwise they're identical
- HI and LO are 32 bits and are used by the multiplication and division instructions
- the PC is 32 bits and is its own thing
- it has lots of instructions: arithmetic, conditional branches, loads and stores, jumps…
- there are actually 3 instruction formats: R, I, and J
- instructions can have 0-3 operands, of which 1 or 2 can be sources, and 0 or 1 can be destinations
- only loads and stores access memory
- it can access 8, 16, or 32-bit values from memory
- the memory address that is accessed is a register + an immediate offset
but the microarchitecture must implement the ISA, so…
CS447

10. Only kinda sorta MIPS we'll use MIPS for context…
but this stuff applies to virtually any architecture.
such as the architecture you'll implement for the project!!
the book doesn't use MIPS either
it uses DLX: a simplified, modernized version of MIPS
the hardware in the book is extremely hand-wave-y (what's jal?)
but they go into way more detail than needed for some things…
CS447

11. The register file Register File
the register file is what holds the GPRs – general-purpose registers
in the instruction add t0, t1, t2, how many registers are read?
how many are written?
are there any instructions that need to read/write more than this?
so it's gonna be a component with one input… D Q en D Q en
and two outputs… D Q en D Q en
etc…
with 32(31?) registers inside.
- dunno why it's called a file... it's likely historical.
- 2 registers are read, and 1 is written.
- aaaand nope. 2 reads/1 write is the max. they designed MIPS that way for speed.
- really don't need a register for $zero, since it's just….. zero……………….
Register File
(and some other logic and control signals but whatever)
CS447

12. + - ×* ÷* & | ^ ~ << >>
The ALU
in MIPS the datapath consists pretty much entirely of the ALU.
ALU
in all the arithmetic and logic (bitwise) instructions, how many operands are there? A + - ×* ÷*
&
what kind of operations do we have to be able to do? | ^ ~ B
<<
>>
- 2. allllways 2.
- we might consider putting mult/div in their own unit, separate from the ALU, but another component of the datapath.
- cause they're slower.
CS447
*multiplication and division are kinda weirdos…

13. What's the next instruction?
what order do these instructions run?
most instructions change the PC to the next address
li s0, 0
top:
move a0, s0
jal print_int
addi s0, s0, 1
blt s0, 5, top
li v0, 10
syscall
print_int:
li v0, 1
syscall
jr ra
control flow instructions can change the PC to a constant…
…or the value from a register…
…or one of two choices, conditionally
CS447

14. The program counter and control
the PC is part of the control: it says what step to do next
Memory
the PC is a memory address
Control
0xAC30 PC
the memory sends back an instruction
0xC0DE
this is an add instruction!
the source regs are t0 and t8…
the control decodes the instruction and tells everything else what to do
but how…?
CS447

15. Instruction Execution
CS447

16. Phases of instruction executionD X M W
Fetch (IF or F)
use PC to get the next instruction from memory
Decode (ID or D)
look at the fetched instruction and set control signals
Execute (EX or X)
wait for data to flow through the datapath
Memory Access (MEM or M)
if it's a load or store, do that
Write-back (WB or W)
if there's a destination register, write the result to it
- every instruction will have a fetch and decode phase.
- almost all instructions have an execute phase (except for a no-op).
- only loads and stores have a memory phase.
- only instructions with destination registers have a write-back phase.
often we can do multiple phases "at the same time"
CS447

17. F D W X M Which parts do what ALU PC Control Register File
Memory
Memory again… I guess?
ALU F D W X M
CS447

18. Single-cycle machine add t0, t1, t2 sb t0, 4(s0)
we'll be talking about a single-cycle machine and building one for project 2
this means each instruction takes one clock cycle to execute
add t0, t1, t2
sb t0, 4(s0)
W: store sum in t0
M: store value in memory
do F, D, X…
do F, D, X…
each instruction ends on the rising edge of the clock
(since that's when the registers store their values)
CS447

19. The big picture
the overall architecture of a computer looks like this:
Inputs
Outputs
Control
Memory
ALU
Registers
Transition Logic
State
CS447

20. There are lots of states
your whole computer is an FSM :^)
with 4GB RAM, bit registers, plus some more registers in there, and all the input/output devices have memory and regs…
we're talking somewhere on the order of uhhhhh
states
it's a finite number of states but it's so ridiculously huge that it's practically infinite
take 1511 to learn about the limits and capabilities of various kinds of computational structures!
CS447

21. A Thing about memory
CS447

22. ☢️ Structural Hazards ☢️
how many RAMs does your computer have? one or two?
if we try to do lw t0, (s0) with one memory in a single cycle…
Instruction Address
Instruction PC
Memory
Control
Load word address…?
Loaded word…??
what about sw?!?
- in contrast to the register file, which can.
- a read port requires "linear space" in the size of the memory.
- for the register file, there are only 32 addresses, so it's an acceptable tradeoff.
- for memory, it's impractical.
we can't really do this… memory hardware can't read from two addresses at the same time
CS447

23. Von Neumann vs Harvard
one way to solve this problem is to have two memories
this is a Harvard Architecture
Instruction Memory PC
Control
Register File
ALU
Data Memory
a Von Neumann Architecture has one memory for both things
"Von Neumann" is 2 words for 1 memory… "Harvard" is 1 word for 2 memories…
CS447

24. Multi-cycle lw t0, (s0) PC Memory
a Von Neumann machine has one memory, but uses multiple clock cycles to execute each instruction
lw t0, (s0)
Cycle 1:
Instruction Address
Instruction PC
Memory
Control
Loaded word
Cycle 2:
Load word address
multi-cycle machines are by far the most common today
but they're more complex…
CS447