1. Horizontally Partitioned Hybrid Main Memory with PCM
Santiago Bock
Daniel Mossé

2. Phase Change Memory (PCM)
Emerging memory technology
Non-volatile (material changes)
Smaller cells than DRAM (less costly)
Cheap/fast reads, expensive/slow writes (melts material)
Possible DRAM replacement
Read Speed
Write Speed
Read Energy
Write Energy
Standby Power
Endurance
DRAM
Fast
Low
High
PCM
Slow

3. Horizontal Hybrid Memory
Small DRAM with large PCM
Horizontal (no “cached” data)
Single address space partitioned into DRAM and PCM
Operating system manages contents
Challenges:
What is the best migration policy?
How can hardware monitors collect information about memory accesses?
How can hardware support migration?
Allocation policy refers to how pages are allocated to either DRAM or PCM.
Migration policy refers to deciding what pages to migrate (and when) to get to a certain allocation.

4. The Simulator Trace Reader Trace Reader Allocation Policy Memory
Manager
CPU
CPU
Migration Policy
Cache
Cache
Shared Cache
Simulation Engine
The Trace Reader reads data from several files and converts it into a trace of memory accesses performed by a processor.
The Hybrid Memory decides where memory accesses go (either DRAM or PCM), and performs migrations of pages.
The Memory Manager performs the translation of virtual to physical address for each access made by a CPU. It also allocates memory based on the Allocation Policy, and migrates pages based on the Migration Policy.
The Simulation Engine is used by all other components to schedule events in the future, and is in charge of executing these events when their time comes up.
Hybrid Memory
DRAM
PCM

5. Basic Knowledge Needed
Computer Architecture
Modern processors and caches
TLB
DRAM
Operating Systems
Virtual memory
Memory management
Programming
C++
Scripting

6. Projects Trace Generation Large Scale Study Simulator Development
Installation of new benchmarks
Large Scale Study
More benchmarks
More parameters
More policies
Simulator Development
New mechanisms and policies
More accurate memory model
Faster simulation