1. EECS 362 – Presentation One
DLX Instruction Set: Jump/Branch

2. Available Instructions
J-Type: bits 3-5 opcode; 6-31 offset
J and JAL
I-Type: bits 0-5 opcode; 6-10 rs; rd; immediate
JR, JALR, BEQZ, BNEZ, BFPT, BFPF
All jumps and branches have one instruction delay

3. Conditional Branches
Instructions do not store return address information
These branches cannot be used as a procedure call
Target address sign extends 16-bit name field to 32-bit sign value
Adds sign value to PC + 4 to get the next instruction

4. BEQZ & BNEZ Instructions may be based on the value in any GPR
BEQZ branches when the source register is zero
BNEZ branches when the source register is not equal to zero

5. BFPT & BFPF
Instructions are based on the contents of the floating point status register, FPSR
BFPT branches when FPSR contains ‘1’ or ‘true’
BFPF branches when FPSR contains ‘0’ or ‘false’

6. J & JR
J branches are made by sign extending the 26-bit name field to the 32-bit signed value. Add to PC + 4.
JR branch target addresses may be in GPRs
J & JR do not attempt to store return address information

7. JAL & JALR
JAL branches are made by sign extending the 26-bit name field to the 32-bit signed value. Add to PC + 4.
JALR branch target addresses may be in GPRs
Both place the address of the instruction after the delay slot (PC + 8) into GPR31
These can then be used for procedure calls