1. The Interconnect, Control, and Instruction Decoding
CS/COE 0447
Jarrett Billingsley

2. Class announcements
shhhhhebang
CS447

3. The Interconnect
CS447

4. Gotta keep em separated interconnected
we've got pieces of a CPU, but they don't operate in isolation
we gotta hook em together. but which parts hook to which?
the instructions in the ISA tell you what has to connect to what.
PC that can branch and jump
Register File
ALU
Data Memory
Instruction Memory
CS447

5. Slowly coming together
if we look at all the different instructions we want to support, we'll start to get an idea of what data goes where
sub v0, t0, t1
sw s0, 4(t3)
Register File
ALU t0 t1 v0 -
Data Memory
Register File
ALU s0 t3 + 4
Data
Address
jal move_ball
ALU?
Register File PC + 4 ra
address of move_ball
how do we make all these different things happen with one set of hardware…?
CS447

6. PC to the left of me, ALU to the right, here I am
the interconnect lets the CPU parts combine in many ways
it's like the CPU's "circulatory system" – it moves data around
think about which instructions move data between which parts…
Register File
Data Memory PC
jal
stores jr
loads
Instruction Memory
li (immediate)
add, sub, etc.
ALU
addi, ori etc.
it's starting to take shape…
CS447

7. A little technique: an interconnect matrix
you can make a table to keep track of what things connect to what.
Does the data flow from here…
now consider all the instructions your CPU should support, and mark the cells accordingly.
…to here?
ALU PC
Regs IM DM sw j lw
beq √
add, sub, and, or √ √ √ √ jr
li?
jal
any component (column) with multiple things coming into it will need a MUX.
(huh? next slide.) √ √
- idk if this is a thing they do "in the real world" but it's worked for me! √
CS447

8. instruction immediates
Conjunction junction
the interconnect makes choices about which things go where
data from memory
ALU results
instruction immediates
saved PC for jal
only one of these is written to the register file
Register File
so how do we choooooose which thing to write?
now we have a select pin. this is a control signal!
RegDataSrc 2
every MUX in the interconnect needs a control signal.
the book calls this "MemToReg" which is a terrible name and is inconsistent with the rest of the control signal names
CS447

9. Interconnected (MIPS, not your project)
if we want to make a suuuuper simple version of MIPS, we can connect the pieces together like this:
Data
Data Memory
(this version doesn't support jal and li, but that's fiiiine)
RegWrite
MemWrite rd
Register File
Address rs
ALU
how can we use this to implement add? sub? addi? lw? sw? rt
RegDataSrc
ALUOp
ALUSrc
but now we need to, uh, control the control signals.
imm field
- add and sub would turn on RegWrite; set RegDataSrc to use the ALU output; set ALUSrc to use the register; and set ALUOp appropriately.
- addi would do almost the same, except set ALUSrc to use the immediate.
- lw would set ALUSrc to immediate; ALUOp to add; set RegDataSrc to memory; and turn on RegWrite.
- sw would be kinda like lw, but turn on MemWrite instead of RegWrite.
CS447

10. The Forgotten Phase: Operand Fetch
CS447

11. F D X M W O? A little extra step
operand fetch is a phase of instruction execution you might see
it fetches the values to be operated on F D X M W O?
it happens after the instruction is decoded.
where do values have to be for the CPU to operate on them?
in the registers…?
CS447

12. Vestigial in MIPS (and your project), operand fetch is super simple:
Register File
imm field
ALU
this is by design: load-store architectures have very simple operand fetch phases.
why? well…
here it is!
CS447

13. Operand Fetch in x86 inc [eax + ecx*4 + 12]
as a CISC, x86 has some… crazy instructions.
inc [eax + ecx*4 + 12]
this is an effective address calculation.
here's what the CPU has to do for this instruction:
(the brackets mean "access memory.")
multiply ecx by 4
add eax to that
add 12 to that
load a word from that address
add 1 to that value
store that value back into the address
this is operand fetch.
be very glad you won't have to do this for your project.
CS447

14. The Control
CS447

15. 👀 Feeling nervous Control sub v0, t0, t1 Data Memory
the control is what sets the write enables and selects to the appropriate values to make each instruction happen
it's like the CPU's brain and nervous system
c'mon you lazy bums
Control
it does this by reading the instructions.
Register File
awwwww we don't wannaaaa
sub v0, t0, t1 👀
Data Memory
Register file, read t0 and t1, and write to v0. ALU, do subtraction. Interconnect, route the data from the two registers into the ALU and from the ALU into the register file. Data memory, you get to take a break.
ALU
yissssss
CS447

16. Two kinds of control signals
first there are the selects
these go into the select pins of muxes, demuxes, or decoders
they can be any number of bits
then there are the write enables
these tell registers and memory when to store data
they're Booleans - 0 or 1
they often come in pairs!
like RegWrite and RegDataSrc.
they decide what to write and when to write it.
Register File
RegWrite rd 5
RegDataSrc
MemWrite
Data Memory
- and rd decides where! whee!
CS447

17. Gotta write it down sw s0, (t0) add t0, t1, t2 jal func1
write enables are kind of the basis of "things happening in a CPU"
almost every instruction writes something somewhere!
add t0, t1, t2
sw s0, (t0)
writes to memory
writes to t0
jal func1
beq s0, 10, end
might write to the PC
writes to the PC and ra!
if an instruction doesn't write anything, it's a no-op (nop).
(nothing changed? then it's like the instruction never happened.)
what changes when a conditional branch isn't taken?
- nothing. nothing happens. (well the PC increments but that always happens.)
CS447

18. + The control hardware PC Control Instruction Memory
we connected the datapath together; now for the control bits PC
target 4
PCSrc + rt rd
PCSrc rs
immediate
Control
instruction goes in…
Instruction Memory
address goes in…
…control signals come out.
…instruction comes out.
somehow.
ALUSrc
RegWrite
ALUOp
RegDataSrc
MemWrite
CS447

19. Instruction Decoding
CS447

20. "do everything at once, but use only what you need."
Pull 'n' peel
the first step is to split the encoded instruction up
but which instruction format is it? actually, it doesn't matter.
31-26
opcode R 31 26 25 21 20 16 15 11 10 6 5
opcode rs rt rd
shamt
funct 32
instruction
25-21 rs
20-16 rt I 31 26 25 21 20 16 15
opcode rs rt
immediate
15-11 rd 31 26 25
opcode
target J
10-6
shamt
5-0
funct
"do everything at once, but use only what you need."
15-0
immediate
25-0
target
CS447

21. No, really, it's fine, don't worry about it
suppose the encoded instruction was addi s0, s0, -1. 31 26 25 21 20 16 15
opcode rs rt
immediate op rs rt rd
shamt
funct
imm
target 32
0x08
put it through the splitter and…
0x10
addi is an I-type instruction.
0x10
opcode, rs, rt, and immediate will be used.
addi s0,s0,-1
0x1F
0x2210FFFF
0x1F
the rest are bogus and will be ignored. see? it's fiiiiiine
…out come a bunch of values.
0x3F
0xFFFF
0x210FFFF
- how does the CPU know it's an I-type instruction?
- well that's like asking: how does a paper hole puncher "know" how far apart to put the holes?
- it… doesn't. we just designed it to do that.
- the control is as dumb as the rest of the CPU. it's mechanical. it sees opcode 8, it will use those fields.
CS447

22. Making the control work
the control is a boolean function that takes the instruction opcode as its input and outputs the control signals.
in other words, it's a big fat truth table.
I really would not recommend making your control unit like this.
opcode
PCSrc
RegDataSrc
RegWrite
ALUOp …
000000 00
000
000001 01 1
110
000010
010
000011
011
000100 11
000101 10
it's time-consuming, confusing, hard to debug, and hard to change.
you will go insane.
I just made up these numbers. Please don't try to use them.
CS447

23. A more approachable approach
Here's a great use for a decoder: decoding. (huh.)
opcode
<r-type>
<uhh random crap> j
these wires tell you which instruction this is. exactly one of these will be on (true) at once.
jal
beq
bne
blez
now it's just a matter of coming up with the logic for each of the control signals.
bgtz
addi
- to be clear: these signals are 1 if the opcode says "yes it's this instruction" and 0 otherwise.
addiu
for that, it's good to focus on one control signal at a time.
slti
sltiu
CS447

24. <the sound a seal makes>
let's say we want to come up with the MemWrite control signal
which MIPS instructions write to memory? sw
this says, "if we are executing a sw, or a sh, or a sb instruction, we are writing to memory, so turn on its write enable." sh
MemWrite sb
what about multi-bit control signals, like the ALU operation? that might be 3 or 4 bits to select a dozen operations.
there are a few approaches…
CS447

25. The brute-force approach: the MUXtipede
in this approach, you use enormous MUXes to select constants.
opcode
it… works, but it's hard to follow.
ALUOp for opcode 0
ALUOp for opcode 1
ALUOp for opcode 2
ALUOp for opcode 3
ALUOp for opcode 4
ALUOp for opcode 5
ALUOp for opcode 6
ALUOp for opcode 7
ALUOp for opcode 8
ALUOp for opcode 9
ALUOp for opcode A
ALUOp for opcode B
ALUOp for opcode C
it's hard to tell which constant is used for which instruction.
it's also hard to add new instructions.
ALUOp
we can make this more elegant, dammit!
- remember, MUXes are universal… you could make your whole CPU out of em. (please do not.)
CS447

26. Priority Encoders Pri Pri Pri Pri Pri
a priority encoder is kind of the opposite of a decoder.
you give it several 1-bit inputs, and it tells you which one is 1.
Pri 1
Pri 1
if none of the inputs is 1, then it gives you X…
Pri X
Pri 1 2
Pri 1 3
to avoid this, put a constant 1 as the first input.
- putting the 1 as the first input is like saying "else, the output is 0".
CS447

27. Multi-bit control signals
let's say we have these instructions, and these ALU operations.
for each input, ask: which instructions need this ALU operation?
add
addi
sub
subi
and or
0: &
1: |
2: +
3: -
ALUOp 0 is the default, so and is handled. 1
Pri
which instruction(s) need OR (1)? or
ALUOp
add
what about + (2)?
addi
sub
what about - (3)?
subi
think of it like an upside-down if-else-if…
- the numbers of the ALU operations are decided by the MUX in the ALU. in your lab, 0 was +, 1 was -, 2 was *, and 3 was ÷.
- "if the instruction is sub or subi, aluop = 3. else if it's add or addi, aluop = 2. else if it's or, aluop = 1. else, aluop = 0."
CS447