6. Pipeline Principle
A non-pipelined system of combination circuits (A, B, C) that computation requires total of 300 picoseconds.
Comb.
logic A B C
100 ps
Delay = 300 ps / Throughput = 1/300 ps = GOPS
Non-pipelined Diagram
Time
OP1
OP2
OP3
Cannot start new operation until previous one completes
A pipelined version by adding register at each output of the combination circuits.
Additional 20 picoseconds to save result in register.
Begin new operation every 120 ps.
Overall latency increases.
Pipelined Diagram R e g
Clock
Comb.
logic A B C
100 ps
20 ps
Delay = 3x120 ps = 360 ps / Throughput = 1/120 ps = 8.33 GOPS
Time A B C
OP1
OP2
OP3
Up to 3 operations in process simultaneously

7. Non-uniform delays Delay = 3x170 ps = 510 psg
Clock
Comb.
logic B C
50 ps
20 ps
150 ps
100 ps
Delay = 3x170 ps = 510 ps
Throughput = 1/170 ps = 5.88 GOPS A
slowest stage
Time
OP1
OP2
OP3 A B C
Throughput limited by slowest stage (170 ps)
Other stages sit idle for much of the time
Challenging to partition system into balanced stages

13. Individual functions are marked with their delay
Individual functions are marked with their delay. You may apply two-way interleaving on a single component. Other components may not be further divided. Draw lines to indicate where you would insert pipelining flip flops.

14. The two-way interleaving circuit may be represented by:

17. Advantages of Pipelining
The cycle time of the processor is reduced.
It increases the throughput of the system
It makes the system reliable.
Disadvantages of Pipelining
The design of pipelined processor is complex and costly to manufacture.
The instruction latency is more.

20. Fundamental Operation of Retiming
A retiming move in a circuit is caused by moving all of the memory elements at the input of a combinational block to all of its outputs, or vice-versa.
Example: The synthesis tool to move stages to balance combination delay on each side of the registers.

23. Cycle Time - Critical Path Delay + Setup time + FF Delay
T ≥ Tmax + Tsetup +TCTQ
TCTQ
Tsetup
Critical (longest) path ≈ 5 gates
FF propagation delay (TCTQ) time from arrival of clock signal till change at FF output
Longest (critical) path delay is a function of: Total gates + wire delays
For FFs to correctly latch data, input data must be stable during the Setup time (Tsetup) before clock arrives

24. Min Path Delay - Hold Time
For FFs to correctly latch data, input data must be stable during Hold time (Thold) after clock arrives.
Determined by delay of shortest path in circuit Tmin ≥ Thold.
Tmin
Tmin ≥ Thold