1. Sungho Kang Yonsei University
Technology Mapping
Sungho Kang
Yonsei University

2. Outline Introduction Graph Covering and Technology Mapping
Choice of Base Functions
Creating the Subject Graph
The DAG-Covering Problem
Tree Covering by Dynamic Programming
Decomposition
Delay Optimization and Graph Covering

3. Characteristics of Technology Mapping
Introduction
Adapt easily to different libraries
Support irregular collections of logic functions
Handle detailed technology-dependent cost functions
Efficient execution time

4. Graph Covering A set of base functions is chosen Subject graphs
Such as a two-input NAND and an inverter
Subject graphs
The logic equations are optimized in a technology-independent manner and are then converted into a graph where each node is restricted to one of the base functions
Pattern graph
Each graph for a library gate
The logic function for each library gate is also represented by a graph where each node is restricted to one of the base functions
The technology mapping problem is viewed as the optimization problem of finding a minimum cover covering of the subject graph by choosing from the collection of the pattern graphs for all gates in the library

5. Choice of Base Functions
The choice of a set of base function is arbitrary as long as the case function set is functionally complete
The goal is to find the base-function set which provides the highest level of optimization and produces a small set of patterns
In SIS, a base function set of 2-input NAND and an inverter is used
In DAGON, a base function set of 2-input, 3-input and 4-input NAND gates is used

6. Creating the Subject Graph
Heuristics are used to find an optimal form for the subject graph
These optimizations include algebraic decomposition and Boolean simplification techniques using technology-independent cost functions
The number of nodes in a subject graph
The total number of literals in SOP form
The longest path from an input to an output
The goal of technology-independent optimization should be to find a representation for the circuit which provides a good starting point for DAG-covering
The optimized equations are then transformed into two-input NAND and inverter form in a straightforward manner

7. DAG-Covering Problem DAG-covering-by-DAGs is NP-hard
Exact covering algorithm is based on a branch-and-bound
The complexity is so large that only trivial problems can be solved
DAGON
Partition the subject graph into trees
Cover each tree optimally
Piece the tree-covers into a cover for the subject graph
Its weak points are in the loss of global view due to the step of partitioning into trees
Covers across partition boundaries are not allowed
MIS
Similar to DAGON
Additional covers are exposed by replacing any straight interconnection between gates with a pair of inverters

8. Tree Covering
Tree Covering
Decompose a DAG into trees, by splitting it at the fanout points
Mapping procedure with 2 phases
Pattern matching
Find all possible ways in which library pattern may cover some nodes of the subject tree
Tree covering
Select one optimum matching for each node
Systematic approach to selecting the matchings
Guarantees a cover of minimum cost and is very efficient
Its run time grows linearly with the size of the subject tree
Start from PIs and consider the gates in topological order
Determine the optimum cover of the subtree rooted at the gate output
This does not work for DAGs in general, because there may be conflicting requirements on how to map a node to several gates

9. Decomposition Decomposition is not unique
Balanced tree
Unbalanced tree
The non uniqueness of the decomposition forces us to consider all distinct pattern for the library gates

10. Delay Optimization Minimum delay optimization
The unique set of pin-loads is determined and binning functions are constructed
Obtain an array of solutions at each node of the subject tree, one per bin
The arrival time for each cover for each load value is computed
At each input of the cover, the optimal solution for driving the corresponding pin-load is selected
The final cover is chosen based on the external load at the root of the tree
The cover obtained by this technique is a minimum delay cover
The complexity of the algorithm is still linear but it depends on the number of load-pins and arrival-time bins