1. Rules for Valid and Ready
AXI4-Lite Handshake
Rules for Valid and Ready

2. The Handshake
Data transferred on the rising clock edge when both are high (“The Handshake”)
No combinational path from VALID to READY or vice versa
Means only Moore outputs (and I would register them)

3. Valid before Ready
Once asserted, VALID must remain asserted until The Handshake occurs

4. Ready before Valid Receiver may wait for VALID to assert READY
An “early” READY may decide to deassert before VALID

5. Valid with Ready

6. Streaming
Sender changes data when a handshake occurs (both VALID and READY asserted)