1. Esam Ali Khan M.S. Thesis Defense
King Fahd University of Petroleum & Minerals Dept. of Computer Eng A Two-Dimensional Geometric-Shapes-Based Compression Scheme for Deterministic Testing of Systems-on-a-Chip
Esam Ali Khan
M.S. Thesis Defense

2. Outline Motivation Possible solutions Test compression techniques
Proposed Technique
Used geometric shapes
Proposed encoding algorithm
Test set sorting
Test set partitioning
Encoding process
Decoding process
Software Decoder
Hardware Decoder
Experimental results
Conclusion & Future work

3. Motivation
With today’s technology, complete systems with millions of transistors are built on a single chip
Test data must be stored in tester memory and transferred from tester to chip
Increasing complexity of systems-on-a-chip increases its test data size  increasing cost of testing (time + memory)
Automatic test equipment has limited speed, channel capacity, and memory.
Need for test data reduction is imperative 3

4. Possible solutions Test set compaction Lossless test data compression
Dynamic: during test pattern generation
Static: after generating the test set
Lossless test data compression
Based on BIST and PRG
Based on encoding algorithms (regardless of the internal architecture)

5. Test compression techniques
Statistical coding based on modified Huffman codes [Jas et al., VTS 99]
Encoding based on storing differing bits in replacement word, & decoding based on embedded processor [Jas et al., ICCD 99]
Burrows-wheeler transformation & modified run-length coding [Yamaguchi et al., ITC 97]
Variable-to-block run-length coding, encoding runs of 0’s followed by 1 [Jas et al., ITC 98]
Variable-to-variable run-length coding using Golomb codes [Chandra et al., VTS 2000]
Variable-to-variable run-length coding using FDR codes [Chandra et al., VTS 2001]

6. Proposed technique A novel idea to gain higher compression ratio
A two-dimensional approach
Using primitive geometric shapes
Assumptions
Already compacted
Partially specified test cubes (contain x’s)
Full-scan circuits (reordering is allowed)

7. Used geometric shapes Point: Lines: (x,y) Type1 Type2 Type3 Type4

8. Used geometric shapes (Cont.)
Triangles:
Type1
Type2
Type3
Type4
(x,y) d
Rectangle:
(x,y) d1 d2

9. Proposed encoding algorithm
Test set sorting
Generate clusters of 0’s or 1’s efficiently encoded by geometric shapes
Test set partitioning
Test set partitioned into L segments
Each segment consists of K blocks
Each block is NxN bits
Block encoding
Do not encode block and store actual test data (00)
Encode block as filled with all 0’s (010)
Encode block as filled with all 1’s (011)
Encode 0’s by geometric shapes (10)
Encode 1’s by geometric shapes (11)

10. Test set sorting - criteria
1-distance 1 x
0.0
1.0
0.25 v1
b11
b12
b13
b21
b22
b23 v2
0/1-distance 1 x
1.0
0.0
0.25
0-distance 1 x
1.0
0.0
0.25

11. Test set sorting - examplev1 1 x v2 v3
Original Vectors v2 x 1 v1 v3
Sorted Vectors
0-distance v3 1 x v2 v1
Sorted Vectors
1-distance

12. Test set partitioning 20 8x8 block 8x4 2x8 2x410
x x x x x
x x x x x x
x x x x
x x x x x x
x x x x x
x x 1 1
x x x 1 x 1 1
8x8
block
8x4
2x8
2x4

13. Block encoding process
Check if block can be encoded as filled with all 0’s or with all 1’s
Encode the 1 bits by geometric shapes
Extract all geometric shapes covering 1 bits
Solve a covering problem to select the smallest number of geometric shapes covering the 1 bits
Encode the 0 bits by geometric shapes
Extract all geometric shapes covering 0 bits
Solve a covering problem to select the smallest number of geometric shapes covering the 0 bits
Determine whether to encode the block by geometric shapes or not & which bit to encode

14. Encoding format Test header information Block encoding information
Block size: 2 bits (8x8, 16x16, 32x32)
No. segments: 12 bits
No. blocks per segment: 10 bits
Row remainder: 5 bits
Column remainder: 5 bits
Block encoding information
Block encoded by shapes or not: 1 bit
Encoded bit: 1 bit
No. shapes: 3 bits or 4 bits or 5 bits
Shape type: 2 bits
Shape sub-type: 2 bits
Coordinate: 6 bits or 8 bits or 10 bits
Distance: 3 bits or 4 bits or 5 bits

15. Decoding process Decoding algorithm can be implemented in
Software using an embedded processor on chip
Hardware
Each segment of blocks has to be decoded and stored in memory
Test vectors of a decoded segment are sent to circuit under test
Limitation of decoder is the need for memory to store a segment of blocks
Segment decoding and circuit testing can be done in parallel if memory resources available

16. Software Decoder Output segment
Read Arguments (Block size; # of segments; # of blocks per segment; Row Remainder; Column Remainder)
For each segment
For each block
Read b1b0
Case b1b0
00: read real data
01: read b and fill the block
10: Decode_shapes(0)
11: Decode_Shapes(1)
Output segment

17. Software Decoder (Cont.)
Decode_Shape(b)
Read # of shapes (log2 N –3)
For each shape
Read shape type (b1b0)
Case b1b0
00: read coordinate and write point
01: read sub-type; coordinate; distance and fill line
10: read sub-type; coordinate; distance and fill triangle
11: read coordinate;distance1; distance2 and fill rectangle

18. Hardware Decoder Designed, modeled and verified using VHDL Consists of
A Finite State Machine (FSM)
A data path
The FSM consists of 62 states

20. Hardware Decoder (Cont.)
Data Path:
Two shift registers
One (12-bit )
One (4-bit)
Five registers
Two (10-bit)
Three (5-bit)
One flip-flop (D-FF)
Eight counters
One (12-bit)
One (10-bit)
One (7-bit)
Five (5-bit)

22. Experimental results Benchmark circuits Test sets Compression ratio
Largest ISCAS 85 and full-scanned versions of ISCAS 89 circuits
Test sets
Dynamic compaction by Mintest [Hamzaoglu & Patel, ICCAD 98]
Static compaction by Mintest
Relaxed to get the x’s
Compression ratio
(# Original Bits - # Compressed Bits) / # Original Bits
All results have been verified using fault simulation

23. Factors affecting Comp. Ratio
X-weight
0.25, 0.5, 1.0
Sorting criteria
0-distance, 1-distance, and 0/1-distance
Block sizes
8x8, 16x16, and 32x32
Greedy vs. Optimal sorting
Size of the test set

24. Compression results for different x-weight

25. Compression results for different sorting criteria (8x8 block)

26. Compression results for different block sizes (0/1-distance)

27. Greedy vs. Optimal sorting

28. Impact of test set on compression
Circuit
Orig. Bits
Comp. Ratio
Comp. Bits
s5378
23754
57.94
9991
20758
51.551
10057
s9234
39273
57.22
16801
25935
43.451
14666
s13207
165200
86.628
22091
163100
85.012
24445
s15850
76986
70.188
22952
57434
60.32
22790
s35932
28208
78.123
6171
21156
25.78
15702
s38417
164736
62.226
62228
113152
46.497
60540
s38584
199104
65.594
68504
161040
65.944
54844

29. Timing performance
Timing of the encoder (in Secs; PII 350 MHz; 32MB RAM )

30. Timing performance (Cont.)
Timing of the decoder
Software decoder (negligible)
Hardware Decoder (500 MHz clock)

31. Comparison with Golomb & FDR codes

32. Percentage of real-data blocks

33. Conclusion
Proposed a novel, very efficient test compression/ decompression scheme for testing systems-on-a-chip
Technique based on encoding test data by geometric shapes
Exploits test vector reordering, partitioning, type of encoded bit, and whether or not to encode a block
Very high compression ratio achieved
Best compression ratio reported and significantly higher than published results
Decoder requires memory to store a test segment

34. Future work Enhance compression ratio by A better sorting scheme
A hybrid scheme to exploit real-data blocks
FDR is a good candidate

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