1. Instructor: Dr. Phillip Jones
CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/24/2011 (Course Overview)
Instructor: Dr. Phillip Jones
Reconfigurable Computing Laboratory
Iowa State University
Ames, Iowa, USA

2. Class Introduction Class Survey (by next class, phjones@iastate.edu)
Background (year in school, C programming, VHDL/Verilog, EE/CPRE background, ISU login ID)
What would you like to get from this class
Syllabus
Course Expectations
Reinforce research fundamentals
Asking the right question
VHDL handbook (source Synplicity)
(quick ref)
VHDL online tutorials

3. What you should learn
Basic objectives and topics covered in this class.
VDHL is NOT a programming language. It is a means to describe hardware.

4. Main topics Basic components of an FPGA (Chapter 1)
Agenda
1. Overview (6 Weeks)
a. Reconfigurable HW
b. VHDL
2. Computation Models & Architectures
(4 Weeks)
3. Mapping logic to FPGAs
(2 Weeks)
4. Case Studies (1 Week)
Basic components of an FPGA (Chapter 1)
Overview of ways in which reconfigurable computing can be integrated into a system (Chapter 2)
Examples of reconfigurable systems (Chapter3)
Managing the reconfiguration of systems? (Chapter 4)

5. Main topics Agenda opcode {+, -, AND, OR} A X B Behavior VHDL: ALU
1. Overview (6 Weeks)
a. Reconfigurable HW
b. VHDL
2. Computation Models & Architectures
(4 Weeks)
3. Mapping logic to FPGAs
(2 Weeks)
4. Case Studies (1 Week)
opcode {+, -, AND, OR} A
ALU X B
Behavior VHDL: ALU
compnt ALU (A,B,opcode,X)
case opcode
when => opPlus
X <= A + B;
when => opSub
X <= A – B;
when => opAND
X <= A and B;
when => opOR
X <= A or B;
end case;
end component;
Structural VHDL: ALU
component ALU (A,B,
opcode, X)
addAB(A,B,Xadd);
subAB(A,B,Xsub);
andAB(A,B,Xand);
orAB(A,B,Xor);
4:1mux(opcode,
Xadd,Xor,
Xand,Xor,X);
end component;

6. Main topics Agenda opcode {+, -, AND, OR} A X B opcode {+, -, AND, OR}
1. Overview (6 Weeks)
a. Reconfigurable HW
b. VHDL
2. Computation Models &
Architectures
(4 Weeks)
3. Mapping logic to FPGAs
(2 Weeks)
4. Case Studies (1 Week)
opcode {+, -, AND, OR} A
ALU X B
opcode {+, -, AND, OR}
ALU 2
Structural VHDL: ALU
component ALU (A,B,
opcode, X)
addAB(A,B,Xadd);
subAB(A,B,Xsub);
andAB(A,B,Xand);
orAB(A,B,Xor);
4:1mux(opcode,
Xadd,Xor,
Xand,Xor,X);
end component;
Xadd
addAB
4:1
Mux A
Xsub
subAB X
andAB
Xand B
orAB
Xor

7. Main topics Abstraction that allows Reasoning about computation
Agenda
1. Overview (6 Weeks)
a. Reconfigurable HW
b. VHDL
2. Computation Models & Architectures
(4 Weeks)
3. Mapping logic to FPGAs
(2 Weeks)
4. Case Studies (1 Week)
Abstraction that allows
Reasoning about computation
Correctness
Extraction of parallelism
Transformations for optimization
Guarantee Properties
FPGA
Memory
CPU

8. Main topics Abstraction that allows Reasoning about computation
Agenda
1. Overview (6 Weeks)
a. Reconfigurable HW
b. VHDL
2. Computation Models & Architectures
(4 Weeks)
3. Mapping logic to FPGAs
(2 Weeks)
4. Case Studies (1 Week)
Abstraction that allows
Reasoning about computation
Correctness
Extraction of parallelism
Transformations for optimization
Guarantee Properties
Memory
Function 2
Function 1
Function 4
Function 3

9. Main topics Abstraction that allows Reasoning about computation
Agenda
1. Overview (6 Weeks)
a. Reconfigurable HW
b. VHDL
2. Computation Models & Architectures
(4 Weeks)
3. Mapping logic to FPGAs
(2 Weeks)
4. Case Studies (1 Week)
Abstraction that allows
Reasoning about computation
Correctness
Extraction of parallelism
Transformations for optimization
Guarantee Properties
Function 1
Memory
Memory
Function 2
Memory
Function 5
Function 3
Memory
Function 4
Memory

10. Main topics Streaming Applications Data Parallel Applications
Agenda
1. Overview (6 Weeks)
a. Reconfigurable HW
b. VHDL
2. Computation Models & Architectures
(4 Weeks)
3. Mapping logic to FPGAs
(2 Weeks)
4. Case Studies (1 Week)
Streaming Applications
Data Parallel Applications
Fix/Floating Point Computations
Evolvable Hardware
Performance Trade-offs

11. Main topics Agenda X <= A+B; X <= A xor B; X <= A and B;
1. Overview (6 Weeks)
a. Reconfigurable HW
b. VHDL
2. Computation Models & Architectures
(4 Weeks)
3. Mapping logic to FPGAs
(2 Weeks)
4. Case Studies (1 Week)
X <= A+B;
X <= A xor B;
X <= A and B;
X <= A or B; A X A X A X
addAB
xorAB
andAB A X
orAB B B B B
A B X
A B X
A B X
A B X
0 0
0 1
1 0
1 1 1
0 0
0 1
1 0
1 1 1
0 0
0 1
1 0
1 1 1
0 0
0 1
1 0
1 1 1
2-input Look Up Tables (LUTs)
FPGA
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT
LUT

12. Main topics Agenda X <= A+B; X <= A xor B; X <= A and B;
1. Overview (6 Weeks)
a. Reconfigurable HW
b. VHDL
2. Computation Models & Architectures
(4 Weeks)
3. Mapping logic to FPGAs
(2 Weeks)
4. Case Studies (1 Week)
X <= A+B;
X <= A xor B;
X <= A and B;
X <= A or B; A X A X X X
addAB
xorAB A
andAB A
orAB B B B B
A B X
A B X
A B X
A B X
0 0
0 1
1 0
1 1 1
0 0
0 1
1 0
1 1 1
0 0
0 1
1 0
1 1 1
0 0
0 1
1 0
1 1 1
2-input Look Up Tables (LUTs)
FPGA
LUT
addAB
LUT
LUT
LUT
LUT
LUT
xorAB
andAB
LUT
LUT
LUT
LUT
orAB
LUT
LUT

13. Main topics Lectures on interesting uses of FPGAs.
Agenda
1. Overview (6 Weeks)
a. Reconfigurable HW
b. VHDL
2. Computation Models & Architectures
(4 Weeks)
3. Mapping logic to FPGAs
(3 Weeks)
4. Case Studies (1 Week)
Lectures on interesting uses of FPGAs.
Ideally covering topics that the class would
like to learn more about.
Please give suggestions as the semester
progresses.

14. Machine Problems (MPs)
Agenda
1. Platform Introduction
2. Network String Matching
3. Image: PPC coprocessor
4. Final Projects(~6 weeks)

15. Machine Problems (MPs)
Agenda
1. Platform Introduction
2. Network String Matching
3. Image: PPC coprocessor
4. Final Projects(~6 weeks)
ML507

16. Machine Problems (MPs)
Agenda
1. Platform Introduction
2. Network String Matching
3. Image: PPC coprocessor
4. Final Projects(~6 weeks)

17. Machine Problems (MPs)
Agenda
1. Platform Introduction
2. Network String Matching
3. Image: PPC coprocessor
4. Final Projects(~6 weeks)
FPGA PC
Echo.vhd
Serial
UART

18. Machine Problems (MPs)
Agenda
1. Platform Introduction
2. Network String Matching
3. Image: PPC coprocessor
4. Final Projects(~6 weeks)
FPGA PC
Echo.vhd
(Modify to capitalize only
(a-z))
Serial
UART

19. Machine Problems (MPs)
Agenda
1. Platform Introduction
2. Network String Matching
3. Image: PPC coprocessor
4. Final Projects(~6 weeks)
FPGA PC
Echo.vhd
Ethernet
(UDP/IP)

20. Machine Problems (MPs)
Agenda
1. Platform Introduction
2. Network String Matching
3. Image: PPC coprocessor
4. Final Projects(~6 weeks)
FPGA PC
Echo.vhd
(Modify to count strings (e.g. corn!))
Ethernet
(UDP/IP)

21. Machine Problems (MPs)
Agenda
1. Platform Introduction
2. Network String Matching
3. Image: PPC coprocessor
4. Final Projects(~6 weeks)
FPGA
Power PC PC
Display.c
Ethernet
(UDP/IP)
User Defined Instruction
VGA
Monitor

22. Machine Problems (MPs)
Agenda
1. Platform Introduction
2. Network String Matching
3. Image: PPC coprocessor
4. Final Projects(~6 weeks)
FPGA
Power PC PC
Display.c
Ethernet
(UDP/IP)
User Defined Instruction
VGA
Monitor

23. Machine Problems (MPs)
Agenda
1. Platform Introduction
2. Network String Matching
3. Image: PPC coprocessor
4. Final Projects(~6 weeks)
FPGA
Power PC PC
Display.c
Ethernet
(UDP/IP)
User Defined Instruction
VGA
Monitor

24. Machine Problems (MPs)
Agenda
1. Platform Introduction
2. Network String Matching
3. Image: PPC coprocessor
4. Final Projects(~6 weeks)
Choose your own topic
Groups of 3-4 (maybe 5 for case by case)
Encouraged to take on aggressive projects

25. Review Syllabus Objects Expectations Grading breakdown
MP grading policy: (more flexible for Distance Students)
Up to 5% added for early completion (Fri Midnight)
-5% after Fri Midnight
-10% additional after Monday Midnight
-10% additional after Tue Midnight
After Wed Midnight will make a note.

26. What is Reconfigurable Computing?
Ask wiki:
Computing on a medium that is not fixed
Examples:
rDPA (course grain reconfiguration)
FPGA (fine grain reconfiguration)
General Purpose Processor (not really) underlining hardware typical executes a relatively small fixed instruction set.

27. What are rDPAs? rDPA: reconfigurable Data Path Array
Function Units with programmable interconnects
Example
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU

28. What are rDPAs? rDPA: reconfigurable Data Path Array
Function Units with programmable interconnects
Example
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU

29. What are rDPAs? rDPA: reconfigurable Data Path Array
Function Units with programmable interconnects
Example
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU
ALU

30. What are FPGAs? FPGA: Field Programmable Gate Array
Sea of general purpose logic gates
CLB
Configurable Logic Block

31. What are FPGAs? FPGA: Field Programmable Gate Array
Sea of general purpose logic gates
CLB
CLB
CLB
Configurable Logic Block
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB

32. What are FPGAs? FPGA: Field Programmable Gate Array
Sea of general purpose logic gates
CLB
CLB
Configurable Logic Block
CLB
CLB
CLB
CLB
CLB
CLB

33. Some FPGA Details
CLB
CLB
CLB
CLB

34. Some FPGA Details CLB CLB CLB 4 input Look Up Table 0000 0001 1110
1111
ABCD Z Z A
LUT B C D

35. Some FPGA Details CLB CLB CLB Z A LUT B C D ABCD Z 0000 0001 1110 11111 A
AND Z
4 input Look Up Table B C D

36. Some FPGA Details CLB CLB CLB Z A LUT B C D ABCD Z 0000 0001 1110 11111 A OR Z
4 input Look Up Table B C D

37. Some FPGA Details CLB CLB CLB Z A LUT B C D ABCD Z B X000 X001 X1101 Z
4 input Look Up Table C
2:1
Mux D

38. Some FPGA Details
CLB
CLB
CLB Z A
LUT B C D

39. Some FPGA Details CLB CLB PIP Programmable Interconnection Point CLB Z
LUT
DFF B C D

40. Some FPGA Details CLB CLB PIP Programmable Interconnection Point CLB Z
LUT
DFF B C D

41. FPGA Usage Models Partial Reconfiguration Fast Prototyping System on
Experimental ISA
Experimental Micro
Architectures
Run-time adaptation
Run-time Customization
CPU + Specialized HW
- Sparc-V8 Leon
Partial
Reconfiguration
Fast
Prototyping
System on
Chip (SoC)
Parallel
Applications
Full
Reconfiguration
Image Processing
Computational
Biology
Remote Update
Fault Tolerance

42. Application Area for Acceleration

43. Development Platform Overview
ML507 Evaluation Platform User Guide (pgs )

44. Machine Problem 1 (MP1) Short Overview
Assigned Fri (8/27), Due Friday (9/10).
Purpose: Make sure you can run the tools. Very light VHDL coding.
Primary Tasks:
Run the echo circuit without modifications
Run the echo circuit with a modification to convert lower case ASCII characters to upper case.
Distance Students: Test using NX for remotely access xilinx.ece.iastate.edu. You can download the NX client from:
For Windows:
For Linux:
For MAC OS:
For Solaris:

45. VHDL basics VHDL: (V)HSIC (H)ardware (D)escription (L)anguage
VHSIC: (V)ery (H)igh (S)peed (I)ntegrated (C)ircuit
It is NOT a programming language!!!
It is a Hardware Description Language (HDL)
Conceptually VERY different form C,C++
Some links to VHDL tutorials
(quick ref)

46. Some Key Differences from C
C is inherently sequential (serial), one statement executed at a time
VHDL is inherently concurrent (parallel), many statements execute (simulate) at a time

47. Some Key Differences from C
C example
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A = B + C
X = Y + Z
Ans = A + X
A <= B + C
X <= Y + Z
Ans <= A + X
Current Values:
A = 1
B = 1
C = 1
X = 1
Y = 1
Z = 1
Ans = 1
Current Values:
A = 1
B = 1
C = 1
X = 1
Y = 1
Z = 1
Ans = 1

48. Some Key Differences from C
C example
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A = B + C
X = Y + Z
Ans = A + X
A <= B + C
X <= Y + Z
Ans <= A + X
Current Values:
A = 2
B = 1
C = 1
X = 1
Y = 1
Z = 1
Ans = 1
Current Values:
A = 1
B = 1
C = 1
X = 1
Y = 1
Z = 1
Ans = 1

49. Some Key Differences from C
C example
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A = B + C
X = Y + Z
Ans = A + X
A <= B + C
X <= Y + Z
Ans <= A + X
Current Values:
A = 2
B = 1
C = 1
X = 2
Y = 1
Z = 1
Ans = 1
Current Values:
A = 1
B = 1
C = 1
X = 1
Y = 1
Z = 1
Ans = 1

50. Some Key Differences from C
C example
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A = B + C
X = Y + Z
Ans = A + X
A <= B + C
X <= Y + Z
Ans <= A + X
Current Values:
A = 2
B = 1
C = 1
X = 2
Y = 1
Z = 1
Ans = 4
Current Values:
A = 1
B = 1
C = 1
X = 1
Y = 1
Z = 1
Ans = 1

51. Some Key Differences from C
C example
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A = B + C
X = Y + Z
Ans = A + X
A <= B + C
X <= Y + Z
Ans <= A + X
“Simulates in parallel ever delta time step”
Current Values:
A = 2
B = 1
C = 1
X = 2
Y = 1
Z = 1
Ans = 4
Current Values:
A = 1
B = 1
C = 1
X = 1
Y = 1
Z = 1
Ans = 1

52. Some Key Differences from C
C example
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
Snap shot after input change
A = B + C
X = Y + Z
Ans = A + X
A <= B + C
X <= Y + Z
Ans <= A + X
“Simulates in parallel ever delta time step”
Current Values:
A = 2
B = 1
C = 1
X = 2
Y = 1
Z = 1
Ans = 4
Current Values:
A = 1
B = 1
C = 1
X = 1
Y = 1
Z = 1
Ans = 1

53. Some Key Differences from C
C example
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A = B + C
X = Y + Z
Ans = A + X
A <= B + C
X <= Y + Z
Ans <= A + X
“Simulates in parallel ever delta time step”
Current Values:
A = 2
B = 1
C = 1
X = 2
Y = 1
Z = 1
Ans = 4
Current Values:
A = 2
B = 1
C = 1
X = 2
Y = 1
Z = 1
Ans = 2

54. Some Key Differences from C
C example
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A = B + C
X = Y + Z
Ans = A + X
A <= B + C
X <= Y + Z
Ans <= A + X
“Simulates in parallel ever delta time step”
Current Values:
A = 2
B = 1
C = 1
X = 2
Y = 1
Z = 1
Ans = 4
Current Values:
A = 2
B = 1
C = 1
X = 2
Y = 1
Z = 1
Ans = 2
Different

55. Some Key Differences from C
C example
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
Snap shot after input change
A = B + C
X = Y + Z
Ans = A + X
A <= B + C
X <= Y + Z
Ans <= A + X
“Simulates in parallel ever delta time step”
Current Values:
A = 2
B = 1
C = 1
X = 2
Y = 1
Z = 1
Ans = 4
Current Values:
A = 2
B = 1
C = 1
X = 2
Y = 1
Z = 1
Ans = 2

56. Some Key Differences from C
C example
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A = B + C
X = Y + Z
Ans = A + X
A <= B + C
X <= Y + Z
Ans <= A + X
“Simulates in parallel ever delta time step”
Current Values:
A = 2
B = 1
C = 1
X = 2
Y = 1
Z = 1
Ans = 4
Current Values:
A = 2
B = 1
C = 1
X = 2
Y = 1
Z = 1
Ans = 2

57. Some Key Differences from C
C example
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A = B + C
X = Y + Z
Ans = A + X
A <= B + C
X <= Y + Z
Ans <= A + X
“Simulates in parallel ever delta time step”
Current Values:
A = 2
B = 1
C = 1
X = 2
Y = 1
Z = 1
Ans = 4
Current Values:
A = 2
B = 1
C = 1
X = 2
Y = 1
Z = 1
Ans = 4

58. Corresponding circuit
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + C
X <= Y + Z
Ans <= A + X
“Simulates in parallel ever delta time step”

59. Corresponding circuit
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + C
X <= Y + Z
Ans <= A + X
“Simulates in parallel ever delta time step”
B(1) +
A(1)
C(1) +
Ans(1)
Y(1) +
X(1)
Z(1)

60. Corresponding circuit
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + C
X <= Y + Z
Ans <= A + X
“Simulates in parallel ever delta time step”
B(1) +
A(2)
C(1) +
Ans(2)
Y(1) +
X(2)
Z(1)

61. Corresponding circuit
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + C
X <= Y + Z
Ans <= A + X
“Simulates in parallel ever delta time step”
B(1) +
A(2)
C(1) +
Ans(4)
Y(1) +
X(2)
Z(1)

62. Corresponding circuit (More realistic)
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + C after 2ns
X <= Y + Z after 2ns
Ans <= A + X after 2ns
“Simulates in parallel ever delta time step”
B(1) +
A(1)
C(1)
2ns +
Ans(1)
Y(1) +
2ns
X(1)
Z(1)
2ns

63. Corresponding circuit (More realistic)
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + C after 2ns
X <= Y + Z after 2ns
Ans <= A + X after 2ns
“Simulates in parallel ever delta time step”
B(1) +
A(2)
C(1)
2ns +
Ans(2)
Y(1) +
2ns
X(2)
Z(1)
2ns

64. Corresponding circuit (More realistic)
VHDL example
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + C after 2ns
X <= Y + Z after 2ns
Ans <= A + X after 2ns
“Simulates in parallel ever delta time step”
B(1) +
A(2)
C(1)
2ns +
Ans(4)
Y(1) +
2ns
X(2)
Z(1)
2ns

65. Typical Structure of a VHDL File
LIBRARY ieee;
ENTITY test_circuit IS
PORT(B,C,Y,Z,Ans);
END test_circuit;
ARCHITECTURE structure OF test_circuit IS
signal A : std_logic_vector(7 downto 0);
signal X : std_logic_vector(7 downto 0);
BEGIN
A <= B or C;
END
Include Libraries
Define component name and
Input/output ports
Declare internal
signals,
components
Implement components
functionality

66. Next Lecture
Basic components of an FPGA
VHDL overview cont.

67. Questions/Comments/Concerns

68. Fast Prototyping Fast Prototyping System on Chip (SoC) Partial
Reconfiguration
Parallel
Applications
Full
Reconfiguration

69. Highly Parallel Applications
Fast
Prototyping
System on
Chip (SoC)
Partial
Reconfiguration
Parallel
Applications
Full
Reconfiguration

70. System on Chip (SoC) Fast Prototyping System on Chip (SoC) Partial
Reconfiguration
Parallel
Applications
Full
Reconfiguration

71. Full Reconfiguration Fast Prototyping System on Chip (SoC) Partial
Parallel
Applications
Full
Reconfiguration

72. Partial Reconfiguration
Fast
Prototyping
System on
Chip (SoC)
Partial
Reconfiguration
Parallel
Applications
Full
Reconfiguration