1. CMOS process and MOSFET Parasitic Elements谷航

2. Contents 3.5.5 CMOS Process 3.6.1 Source-Drain Resistance
3.6.2 Source/Drain Junction Capacitance

3. CMOS Process
In a CMOS process both p- and n-channel transistors have to be on the same substrate.This is normally achieved by creating a secondary substrate,called the well or tub,in the main substrate.

4. Another alternative
is to form two separate
wells.This is called a
twin tub CMOS process.

6. Note from this figure,that the CMOS process creates two parasitic bipolar transistors,lateral and vertical.In a n-well process the p+ source,n-well and the p-substrate constitute a vertical pnp transistor while the n-well,p-substrate and n+source form a lateral npn transistor.
They form a feedback loop.The loop gain of this pnpn switch,called silicon controlled rectifier.

7. When the loop gain is greater than one ,the SCR can be switched to a low impedence state with large current conduction(often many miliamperes)
This condition is called latchup.And it can easily destroy a chip.Under certain conditions such as transient currents,ionizing radiations,etc. lateral currents in the well and substrate can forward bias eitter-base junctions of the bipolar transisitors,thus activating the latchup.

8. By reducing Rwell and Rsub,the gain can be below one thus avoiding latchup. The well resistance is normally reduced by forming aretrograde well with a doping profile somewhat similar to that shown in Figure The high doping concentration in the bulk provides a low resistivity path for lateral current,while relatively low doping at the surface maintains high breakdown voltage of the S/D junctions.

10. Epi-CMOS process
For a n-well process a p-epitaxial layr is grown on a p+ substrate .
The heavily doped substrate provides a low resistivity path for lateral substrate currents.The effectiveness of this approach depends on the thickness and bias voltage of the epitaxial layer.
A twin tub CMOS process is far less prone to
latchup compared to a n-well process.

12. Using suitable fabrication and appropriate layout techniques,latchup is generally minimized,although it can never be eliminated.

13. MOSFET Parasitic Elements
The source/drain junction portion of a MOSFET is a parasitic component.These junctions have resistance and capacitances.These parasitice elements limit the drive capability and switching speed of the device and should be minimized.But the effects can not be eliminated.

14. Source-Drain Resistance
The voltage drops across the intrinsic resistances Rs and Rd associated with the source and drain regions,respectively,are negligible compared to the applied voltages.So Rs and Rd are negligible compared to the channel resistance Rch.
L is the channel length

15. However,as the channel length L decreases the series resistance Rs and Rd become appreciable fractions of Rch and cannot be neglected.
Let us see what are the factors which influence Rs and Rd.
Rs=Rsh+Rco+Rsp

17. Rsh is the sheet resistance of the heavily doped source(drain) diffusion region where the current flows along the parallel lines,
Rco is the contact resistance between the metal and the source (drain) diffusion region
Rsp is the spreading resistance due to the current lines crowding near the channel end of the source(drain)

18. S is the distance between the contact via
and the channel region ,ρs is the sheet resistance per square and W is device width.

19. Within the contact area, the voltage drop in the diffused region results in current crowding near the front end of the contanct.This effect results in acontact resistance Rco.
lc is the length of a rectangular contact . ρc is the interfacial specific contact resistivity between the metal and the source (drain)region.In practice ρc is sensitive to the metal-silicon interface preparation procedure.

20. The spreading resistance Rsp arises from the radial pattern of current spreading from the MOSFET channel,which has a thickness of the order of 50 Å.
Tac is the thickness of the surface accumulation layer of length lac in the gate-to-source/drain overlap region .H is the factor that has been found to be in the range of

21. The current is confined to the accumulation layer and then spreads into the bulk,the resistance Rac of this accumulation layer must be added to Rsp.
Rsh and Rsp are invariant with scaling mainly due to increased ρs.

22. All three components of the series resistance have values of the same order of magnitude.

23. More realistic expressions for Rsp have been determined assuming a nonuniform doping profile of the source(drain) junction near the vicinity of the channel end.This results in Rsp and Rac being gate bias dependent.Both these resistances decrease with increaing Vgs.
For MOSFET circuit models bias dependence of Rt is ignored in order to keep current equations simple.

24. Effect of Source/Drain Resistance on Device Transconductance
Both show that gm reduces due to the presence of S/D resistance.
In the saturation region,g’ds=0,so we have

25. Conclusion:the impact of Rs and Rd on gm in the linear region is more pronounced than in the saturation region.That is, the drain current reduction due to Rt(=Rs+Rd) is more pronounced in the linear region compared to the saturation region.

26. Source/Drain Junction Capacitance
The source/drain to substrate boundary is an n+p(p+n) junction.
The capacitance of a pn junction consists of two components,the area component(or bottom-wall capacitance) and periphery component(or side-wall capacitance)
In a MOSFET the S/D doping concentration towards the outer side is different from the inner side.

27. 3 inner side-wall capacitance Cjsw2
A MOSFET junction capacitance is divided into the following three components as shown.
1 bottom-wall capacitance Cjw
2 outer side-wall capacitance Cjsw1
3 inner side-wall capacitance Cjsw2
For submicron devices,due to thinner gate oxides,low junction depth and higher channel doping concentration,the inner side-wall capacitance becomes higher than the outer side-wall capacitance.

29. Thank you!