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Research Progress Fall Present

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Presentation on theme: "Research Progress Fall Present"— Presentation transcript:

1 Research Progress Fall 2009 - Present
Kevin Dwan June 25, 2010 UCLA

2 NEMS Project Collaborators: Goals: UCLA Automation Dejan Markovic
UC Berkeley Elad Alon Tsu-Jae King Liu MIT Vladimir Stojanovic Goals: Automation Innovative Logic UCLA

3 Design Rule Checker (DRC)
Automate verification process CLICKR2: 2 Routing Layers 10 Total Layers On the order of microns SEMATECH: “3” Routing Layers 15 Total Layers Special Layer Rules UCLA

4 Encounter SEMATECH: Layout automation 3 usable routing layers
“2” device types Shared masks with CMOS process Implement “special vias” Electrode ViaContact M2 CMOS Via1 M1 CMOS UCLA

5 Circuits Asynchronous Circuits Balloon Latches C Muller Pipeline
Shift Latch C1 C2 C3 C4 En D Q

6 Muller Pipeline C Element
Circuits Muller C Element Muller Pipeline C Element A B OUT 1 x C

7 Synthesis Synthesis PnR Flow Behavioral Verilog Structural Verilog
Design automation Behavioral Verilog Synthesis Structural Verilog PnR Flow Layout

8 Synthesis Implementation: Challenges: Design automation
Define cells in standard cell library Specify logical and timing behavior Challenges: Tool is designed for CMOS Optimize for timing

9 Synthesis Proposed Solutions: Design automation
Specify Complex Combinational Blocks in library Requires complementary inputs Get tool to recognize tri-state behavior

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