1. 7. Microarchitecture of Superscalars (5) Dynamic Instruction Issue
Dezső Sima
Fall 2006
 D. Sima, 2006

2. Overview 1 The principle of dynamic instruction issue 2 Design space
2.2 Types of issue buffers
2.3 Operand fetch policies
3 Principle of operation of dynamic instruction issue
3.1 Dispatch bound operand fetching
3.2 Issue bound operand fetching
4 Implementation of dynamic instruction issue in superscalars
4.1 The introduction of dynamic instruction issue
4.2 Basic implementation schemes
5 Case examples

3. 1. Principle of dynamic instruction issue (1)
Aim:
To eliminate the issue bottleneck of early (first generation) supercalars

4. 1. Principle of dynamic instruction issue (2)
The issue bottleneck
Icache
I-buffer
Instr. window (3)
Issue
Decode,
check,
Dependent instructions
issue
block instruction issue EU EU
(a): Simplified structure of the mikroarchitecture assuming unbuffered issue
(b): The issue process
Figure 1.1: The principle of dynamic instruction issue

5. 1. Principle of dynamic instruction issue (3)
Eliminating the issue bottleneck Dynamic instruction issue
(shelving, buffered issue)
(a): Simplified structure of the mikroarchitecture assuming buffered issue (shelving)
(b): The issue process
Figure 1.2: Principle of dynamic instruction issue

6. 2. Design space of dynamic instruction issue
2.1 Overview
Dynamic instruction issue
Scope of dynamic instr. issue
Layout of the issue buffers
Operand fetch policy
Instruction issue scheme
Types of issue buffers

7. Reservation stations (RS)
2.2 Types of issue buffers
Types of issue buffers
Reservation stations (RS)
Issue buffers
in the ROB
Individual
RSs
Group
RSs
Central RS FX EU FP FX EU RS FP RS FX EU FP RS FX EU FP
Power1 (1990)
PowerPC 603 (1993)
PowerPC 604 (1995)
Power4 (2001)
Power5 (2004)
K5 (1995)
K7 (1999), K8 (2003)
ES/9000 (1992)
Power2 (1993)
R10000 (1996)
PM1(Sparc64)(1995)
Alpha (1997)
Pentium Pro (1995)
Pentium II (1997)
Pentium III (1999)
Pentium IV (2000)
Pentium M (2003)
Core (2006)
Lightning (1991)p
K6 (1997)

8. Dynamic instruction issue
Scope of buffered issue
Layout of the issue buffers
Operand fetch policy
Instruction issue scheme
Types of issue buffers

9. Operand fetch policies
Dispatch bound
operand fetch policy
Issue bound
operand fetch policy
I-buffer
I-buffer
Decode / Issue
Decode / Issue
Source reg. identifiers
Source reg. identifiers
Dispatch
Dispatch
Reg. file IB IB
Opcodes, destination reg. identifiers
Issue
Source 1 operands OC Rd
Rs1
Rs2 OC Rd
Rs1
Rs2
Source reg. identifiers
Source 2 operands IB Rd
Op1/Rs1
Op2/Rs2 IB
Opcodes, destination
reg. identifiers
Reg. file
Issue OC OC Rd
Op1/Rs1
Op2/Rs2
Source 1 operands
Source 2 operands EU EU EU EU
Rd, result
Figure 2.1: Operand fetch policies

10. 3 Principle of operation of dynamic instruction issue
3.1 Dispatch bound operand fetching (1)
Checking the availability of operands
I-buffer
Decode / Issue
Source reg. identifiers
Dispatch V
Reg. file
Opcodes, destination reg. identifiers
Source 1 operands
Source 2 operands V V V V IB Rd
Op1/Rs1
Op2/Rs2 IB
Issue OC OC Rd
Op1/Rs1
Op2/Rs2 EU EU
Rd, result

11. 3.1 Dispatch bound operand fetching (2)
Updating the issue buffers
I-buffer
Decode / Issue
Source reg. identifiers
Dispatch V
Reg. file
Opcodes, destination reg. identifiers
Source 1 operands
Source 2 operands V V V V IB Rd
Op1/Rs1
Op2/Rs2 IB
Issue OC OC Rd
Op1/Rs1
Op2/Rs2 EU EU
Rd, result

12. 3.2 Issue bound operand fetching
Checking the availability of operands
I-buffer
Decode / Issue
Source reg. identifiers
Dispatch IB IB
Issue OC Rd
Rs1
Rs2 OC Rd
Rs1
Rs2
Source reg. identifiers V
Opcodes, destination
reg. identifiers
Reg. file
Source 1 operands
Source 2 operands EU EU

13. 4. Implementation of dynamic instruction issue in superscalars
4.1 The introduction of dynamic instruction issue
Figure 4.1: The introduction of dynamic instruction issue

14. Basic issue buffer schemes Reservation stations (RS)
4.2 Basic implementation schemes
Basic issue buffer schemes
Reservation stations (RS)
Issue buffers
in the ROB
Types of issue buffers
Individual
RSs
Group
RSs
Central RS
Dispatch
bound
Issue
bound
Dispatch
bound
Issue
bound
Dispatch
bound
Issue
bound
Dispatch
bound
Issue
bound
Operand fetch policy
PowerPC 603 (1993)
PowerPC 604 (1995)
K5 (1995)
PM1(Sparc64) (1995)
Pentium Pro (1995)
Pentium II (1997)
Pentium III (1999)
Power1 (1990)
Power4 (2001)
Power5 (2004)
Nx586 (1994)
K7 (1999), K8 (2003)
ES/9000 (1992)
Power2 (1993)
R10000 (1996)
Alpha (1997)
Pentium IV (2000)
Pentium M (2003)
Core (2006)
Lightning (1991)p
K6 (1997)

15. Individual issue buffers
5. Case example (1)
Individual issue buffers
Figure 5.1: The microarchitecture of the Athlon

16. Individual issue buffers (2)
5. Case example (1)
Individual issue buffers (2)
Decoders
Issue buffers
EUs
Figure 5.2: Integer issue buffers of the K8L
Source: Malich, Y.„AMD's Next Generation Microarchitecture Preview: from K8 to K8L”, Aug

17. Figure 5.3: The microarchitecture of the Alpha 21264
5. Case example (2)
Group issue buffers
Figure 5.3: The microarchitecture of the Alpha 21264
Source: Kessler, R.E. et al. .„The Alpha Microprocessor Architecture”, h18002.www1.hp.com/alphaserver

18. Central reservation station (1)
5. Case example (3)
Central reservation station (1)
Figure 5.3: The microarchitecture of the Core processor
Source: Kanter, D., „Intel’s next Generation Microarchitecture Unveiled”, Real World Tech., 2006 March 9.