1. ADC12J4000, TSW14J10, VC707 Dec 10x

2. Test Setup:
Single tone is given as input to the device.
Test conditions:
Fs = internal 4GHz
Fin = 600MHz
Dec 10
LMF = 222, Lane Rate = Fs * 10 *F/S = 400M * 10 * 2 = 8G
LMK = 2GHz, clock dist mode
VC707 Ref clock = 400MHz (Lane rate/20, /4 for LMK)
VC707 Core clock = 200MHz (Lane rate /40, /8 for LMK)
Lane Rate = 8G
V2p8 firmware

3. On ADC GUI, load the values as shown below

4. On ADC GUI, load the values as shown below

5. On ADC GUI, load the Preset 0 Frequency value as shown below

6. In Low Level View tab, set LMK04828 address 0x110 to 0x05 to set VC707 REFCLK = 400MHz

7. In Low Level View tab, set LMK04828 address 0x100 to 0x0A for VC707 Core CLK = 200MHz

8. Open HSDCD Pro, select “ADC12J4000_D4_DDR”, Enter “1G” for ADC Output Data Rate

9. Capture results using a 600MHz input tone