1. Accelerating Dependent Cache Misses with an Enhanced Memory Controller
Milad Hashemi, Khubaib, Eiman Ebrahimi, Onur Mutlu, Yale N. Patt
Tuesday June 21: Session 7A, 3:30pm

2. Memory Access Latency Multiprocessor DRAM
The latency of accessing main memory is made up of two parts:
Multiprocessor
DRAM

3. Memory Access Latency Multiprocessor DRAM
The latency of accessing main memory is made up of two parts:
DRAM access latency
Multiprocessor
DRAM

4. Memory Access Latency Multiprocessor DRAM
The latency of accessing main memory is made up of two parts:
DRAM access latency
On-chip latency
Multiprocessor
DRAM

5. On-Chip Delay

6. Dependent Cache Misses
LD [R3] -> R5

7. Dependent Cache Misses
LD [R3] -> R5
ADD R4, R5 -> R9

8. Dependent Cache Misses
LD [R3] -> R5
ADD R4, R5 -> R9
ADD R9, R1 -> R6

9. Dependent Cache Misses
LD [R3] -> R5
ADD R4, R5 -> R9
ADD R9, R1 -> R6
Cache Miss
LD [R6] -> R8

10. Compute Capable Memory Controller

11. Effective Memory Access Latency Reduction

12. Effective Memory Access Latency Reduction

13. Accelerating Dependent Cache Misses with an Enhanced Memory Controller
Milad Hashemi, Khubaib, Eiman Ebrahimi, Onur Mutlu, Yale N. Patt
Tuesday June 21: Session 7A, 3:30pm