1. Lecture 9. MIPS Processor Design – Decoding and Execution
2010 R&E Computer System Education & Research
Lecture 9. MIPS Processor Design – Decoding and Execution
Prof. Taeweon Suh
Computer Science Education
Korea University

2. Data in your program, Stack, Heap
Instruction
Memory
MIPS CPU
Address Bus
Data Bus
Data
Overview of CPU Design
mips_tb.v (testbench)
mips_cpu_mem.v
reset
mips_cpu.v
imem.v
(Instruction Memory)
Address
Decoding
fetch, pc
clock
Binary (machine code)
Instruction
Register File
ALU
Memory Access
dmem.v
(Data Memory)
Address
DataOut
Data in your program, Stack, Heap
DataIn

3. Increment by 4 for next instruction 32-bit register (flip-flops)
Instruction Fetch
MIPS CPU Core
Increment by 4 for next instruction 4
Add
Instruction Memory
Address
Out 32 PC
reset
clock
instruction
32-bit register (flip-flops)
What is PC on reset?
MIPS initializes the PC to 0xBFC0_0000
For the sake of simplicity, let’s initialize the PC to 0x0000_0000 in our design
How about x86 and ARM?
x86 reset vector is 0xFFFF_FFF0. BIOS ROM is located there
ARM reset vector is 0x0000_0000

4. Instruction Decoding Instruction Decoding
Separate the fetched instruction into the fields (according to the instruction types: R, I, and J types)
Opcode and funct fields determine which operation the instruction wants to do
Control logic needs to be designed to supply control signals to appropriate components (such as ALU and register file) inside CPU
Operands
Register addresses in the instruction are sent to the register file
Immediate field is either sign-extended or zero-extended depending on the instruction

5. Instruction Decoding Schematic
MIPS CPU Core
Control Unit
Opcode
funct
RegWrite
Register File
wa[4:0]
ra1[4:0]
ra2[4:0]
rd1 32
rd2 wd
RegWrite R0 R1 R2 R3
R30
R31 …
instruction PC
Add 4
reset
clock
Instruction Memory
Address
Out 16 32
Sign or zero-extended
imm 32

6. Register File in Verilog
module regfile(input clk,
input RegWrite,
input [4:0] ra1, ra2, wa,
input [31:0] wd,
output [31:0] rd1, rd2);
reg [31:0] rf[31:0];
// three ported register file
// read two ports combinationally
// write third port on rising edge of clock
// register 0 hardwired to 0
clk)
if (RegWrite) rf[wa] <= wd;
assign rd1 = (ra1 != 0) ? rf[ra1] : 0;
assign rd2 = (ra2 != 0) ? rf[ra2] : 0;
endmodule
Register File wa
ra1[4:0]
ra2[4:0]
32 bits
rd1 32 5
rd2 wd
RegWrite R0 R1 R2 R3
R30
R31 …

7. Sign/Zero Extension in Verilog
Why declares it as reg?
Is it going to be synthesized as registers?
Is this logic combinational or sequential logic?
module sign_zero_ext(input sign_ext,
input [15:0] a,
output reg [31:0] y);
begin
if (sign_ext) y <= {{16{a[15]}}, a};
else y <= {{16{1'b0}}, a};
end
endmodule 16 32
Sign or zero-extended
a[15:0] = imm
y[31:0]
sign_ext

8. Instruction Execution #1
Execution of the arithmetic and logical instructions
R-type arithmetic and logical instructions
Examples: add, sub, and, or ...
Operand sources
2 Operands from the register file
I-type arithmetic and logical instructions
Examples: addi, andi, ori ...
1 operand from the register file
1 operand from the immediate field
opcode rs rt rd sa
funct
add $t0, $s1, $s2
destination register
opcode rs rt
immediate
addi $t0, $s3, -12

9. Instruction Execution Schematic – Arithmetic and Logical Instructions
MIPS CPU Core
Control Unit
Opcode
funct
ALUSrc
RegWrite
Register File
wa[4:0]
ra1[4:0]
ra2[4:0]
rd1 32
rd2 wd
RegWrite R0 R1 R2 R3
R30
R31 …
ALU
ALUSrc
instruction
mux PC
Add 4
reset
clock
Instruction Memory
Address
Out 16 32
Sign or zero-extended
imm 32

10. How to Design Mux in Verilog?
module mux2 (input [31:0] d0, d1,
input s,
output [31:0] y);
assign y = s ? d1 : d0;
endmodule
module mux2 (input [31:0] d0, d1,
input s,
output reg [31:0] y);
begin
if (s) y <= d1;
else y <= d0;
end
endmodule OR
Design it with parameter, so that this module can be used (instantiatiated) in any sized muxes in your design
module datapath(………);
wire [31:0] writedata, signimm;
wire [31:0] srcb;
wire alusrc
// Instantiation
mux2 #(32) srcbmux(writedata, signimm, alusrc, srcb);
endmodule
module mux2 #(parameter WIDTH = 8)
(input [WIDTH-1:0] d0, d1,
input s,
output [WIDTH-1:0] y);
assign y = s ? d1 : d0;
endmodule

11. Instruction Execution #2
Execution of the memory access instructions
lw, sw instructions
opcode rs rt
immediate
lw $t0, 24($s3) // $t0 <= [$s3 + 24]
opcode rs rt
immediate
sw $t2, 8($s3) // [$s3 + 8] <= $t2

12. Instruction Execution Schematic with Memory Access Instructions
MIPS CPU Core
Control Unit
Opcode
funct
MemtoReg
MemWrite
Data Memory
Address
ReadData
WriteData
MemWrite
ALUSrc
RegWrite
Register File
wa[4:0]
ra1[4:0]
ra2[4:0]
rd1 32
rd2 wd R0 R1 R2 R3
R30
R31 …
ALU
ALUSrc
instruction
mux
MemtoReg
mux PC
Add 4
reset
clock
Instruction Memory
Address
Out 16 32
Sign or zero-extended
imm 32
lw $t0, 24($s3) // $t0 <= [$s3 + 24]
sw $t2, 8($s3) // [$s3 + 8] <= $t2

13. Data Memory Verilog Model
module dmem(input clk, MemWrite,
input [31:0] Address,
input [31:0] WriteData,
output [31:0] ReadData);
reg [31:0] RAM[63:0];
assign ReadData = RAM[Address[7:2]];
clk)
begin
if (MemWrite)
RAM[Address[7:2]] <= WriteData;
end
endmodule 32
Data Memory
Address
ReadData[31:0]
WriteDat[31:0]
MemWrite 6
64 words
Word (32-bit)

14. Instruction Execution #3
Execution of the branch and jump instructions
beq, bne, j, jal, jr instructions
opcode rs rt
immediate
beq $s0, $s1, Lbl // go to Lbl if $s0=$s1
Destination = (PC + 4) + (imm << 2)
opcode
jump target
j target // jump
Destination = {PC[31:28] , jump target, 2’b00}

15. Instruction Execution Schematic with “beq” Instruction
MIPS CPU Core
Control Unit
Opcode
funct
branch
PCSrc
zero
Data Memory
Address
ReadData
WriteData
MemWrite
Register File
wa[4:0]
ra1[4:0]
ra2[4:0]
rd1 32
rd2 wd R0 R1 R2 R3
R30
R31 …
ALU
ALUSrc
mux
MemtoReg
instruction
mux
PCSrc
mux
Add
Instruction Memory
Address
Out 16 32
Sign or zero-extended
imm 4
Add
<<2 32 PC
reset
clock
Destination = (PC + 4) + (imm << 2)

16. Instruction Execution Schematic with “j” Instruction
MIPS CPU Core
Control Unit
Opcode
funct
jump
branch
PCSrc
zero
Data Memory
Address
ReadData
WriteData
MemWrite
Register File
wa[4:0]
ra1[4:0]
ra2[4:0]
rd1 32
rd2 wd R0 R1 R2 R3
R30
R31 …
ALU
ALUSrc
mux
MemtoReg
instruction
mux
PCSrc
jump
mux
Add
mux 16 32
Sign or zero-extended
imm
Instruction Memory
Address
Out
<<2 4
Add 26
imm
<<2 32 PC 28
J_addr
reset
clock
PC[31:28]
Destination = {PC[31:28] , jump target, 2’b00}