1. Junctionless Device

2. Introduction
Main purpose: Proposed to improve the processing thermal budget
for nanoscale devices
Key point: fully depleted the channel when the device is turned off
Method: the carrier concentration is identical to the source and drain,
multi-gate and ultra-thin channel
J-P. Colinge, et al. Nature nanotechnology, 2010.

3. Research Status Planar poly-Si JL TFT:
tchannel=10nm, tchannel=8.5nm, Lg=5um,
Improved on current
H-C. Lin, et al. EDL, 2010
Nanowire poly-Si JL TFT: Lg=1 um Improved on current
C-J. Su, et al. EDL, 2011

4. ITO JL TFT: Lg very large Low cost, large capacitor
J. Jiang, et al. APL, 2011

5. Discussion JL device is proposed for the fabricate nanoscale MOSFET
What are the advantages for JL TFTs?
Large on current
Simplicity in fabrication
Implemented in SOP system

6. How to fabricate a JL ITO TFT?

7. Thank you