1. Implementing Combinational
ECE 448
Lab 2
Implementing Combinational
and Sequential Logic
in VHDL
ECE 448 – FPGA and ASIC Design with VHDL
George Mason University

2. Agenda for today
Part 1: Introduction to Lab 2
Part 2: Hands-on Session:
Simulation Using Aldec Active-HDL
Part 3: Lab Exercise 1
Part 4: Lab Exercise 2
Part 5: Demos of Lab 1

3. Part 1 Introduction to Lab 2
ECE 448 – FPGA and ASIC Design with VHDL

4. Discussion of the Block Diagram, Requirements, and Hints

5. Task 1

6. Block Diagram:
BCD_AS

7. Block Diagram: Nines Complementer

8. Task 2

9. Block Diagram: BCD_AS_SEQ

10. Simulation Using Aldec Active-HDL
Part 2
Hands-on Session
Simulation Using Aldec Active-HDL
ECE 448 – FPGA and ASIC Design with VHDL

11. based on the MLU example
Hands-on Session
based on the MLU example
with simple testbench

12. Part 3
Lab Exercise 1
ECE 448 – FPGA and ASIC Design with VHDL

13. Part 4
Lab Exercise 2
ECE 448 – FPGA and ASIC Design with VHDL

14. Part 5
Lab 1 Demos
ECE 448 – FPGA and ASIC Design with VHDL