1. STT-RAM Circuit Design
STT-RAM Cell & Column Circuitry
Fengbo
08/23/2010

2. STT-RAM CELL (2 finger device)
Source contacts are shared by the same column
Gate contacts are shared by the same row
No need to share SL
Min. cell size: F2 (W/L = 750/50 nm)
Wc Depends on W of transistor
Hc = 0.5 um M4

3. Cell Size v.s. Write Current
Wc = Wgate / um
Will build min. size (27.75), 35, 50 F2 cell in the tapeout
Share Source & Gate Contact
Cell Size (F2)
27.75 30 35 40 45 50
Cell Height HC (um)
0.5
Cell Width WC (um)
0.555
0.6
0.7
0.8
0.9 1
W of Transistor (um)
0.75
0.84
1.04
1.24
1.44
1.64
Boosted, IWP (uA)
723
779
884
972
1040
1090
Boosted, IWAP (uA)
410
422
443
458
471
480
5 ns Switching
[J.P. Wang]
3 ns Switching
[J.P. Wang]

4. Column Circuitry 4.84 x 120 um 8-1 Mux
1.5v device induces 4x area overhead in column mux and write circuit
For same amount of writing current, same pitch (256 rows each memory core)
Non-boosted case
Memory core height: 405 um
Column circuit height: um
Total: um
Boosted case with medium oxide device (Our design)
Memory core height: 256 um (63%)
Column circuit height: 120 um (246%)
Total: 376 um
Boosted case with thin oxide device (assume it works)
Memory core height: 256 um
Total:304.75