1. Day 5: September 17, 2010 Restoration
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems
Day 5: September 17, 2010
Restoration
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2. Today How do we make sure logic is robust
Can assemble into any (feed forward) graph
Can tolerate loss and noise
….while maintaining digital abstraction
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3. Outline Two problems Cascade failure Restoration Transfer Curves
Noise Margins
Non-linear
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4. Wire Crossings and Shorts
Wires connected/shorted
Wires not connected
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5. Two Problems Output not go to rail Signals may be perturbed by noise
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6. Output not go to Rail CMOS, capacitive load CMOS, resistive load?
Mostly doesn’t have problem
CMOS, resistive load?
Igd≠0 ?
How close to rail do I need to get?
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7. Wire Resistance
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8. Wire Resistance
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9. Wire Resistance Sanity check Wire twice as long = resistors in series
Wire twice as wide = resistors in parallel
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10. Wire Resistance 1000 mm long wire? 1 cm long wire? Length of die side?
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11. Die Sizes Processor Die Size Transistor Count Process
Core 2 Extreme X mm² 291 Mio. 65 nm
Core 2 Duo E mm² 291 Mio. 65 nm
Core 2 Duo E mm² 291 Mio. 65 nm
Core 2 Duo E mm² 167 Mio. 65 nm
Core 2 Duo E mm² 167 Mio. 65 nm
Pentium D mm² 376 Mio. 65 nm
Athlon 64 FX mm² 227 Mio. 90 nm
Athlon mm² 154 Mio. 90 nm
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12. Implications
What does the circuit really look like for an inverter in the middle of the chip?
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13. Implications
What does the circuit really look like for an inverter in the middle of the chip?
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14. IR-Drop
Since interconnect is resistive and gates pull current off the supply interconnect
The Vdd seen by a gate is lower than the supply Voltage by
Vdrop=Isupply x Rdistribute
Two gates in different locations
See different Rdistribute
Therefore, see different Vdrop
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15. Output not go to Rail CMOS, capacitive load CMOS, resistive load
Mostly doesn’t have problem
CMOS, resistive load
Due to IR drop, “rails” for two communicating gates may not match
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16. Two Problems Output not go to rail Signals may be perturbed by noise
Is this tolerable?
Signals may be perturbed by noise
Voltage seen at input to a gate may not lower/higher than input voltage
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17. Noise Sources?
What did we see in lab when zoomed in on signal transition?
Signal coupling
Crosstalk
Leakage
Ionizing particles
IR-drop in signal wiring
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18. Two Problems Output not go to rail Signals may be perturbed by noise
Is this tolerable?
Signals may be perturbed by noise
Voltage seen at input to a gate may not lower/higher than input voltage
What happens to degraded signals?
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19. Preclass
All 1’s  logical output?
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20. Preclass 1.0 inputs, gate: o=1-AB  output voltage?
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21. Preclass 0.95 inputs, gate: o=1-AB  output voltage?
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22. Degradation Cannot have signal degrade across gates
Want to be able to cascade arbitrary set of gates
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23. Gate Creed Gates should leave the signal “better” than they found it
“better”  closer to the rails
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24. Restoration Discipline
Define legal inputs
Gate works if Vin “close enough” to the rail
Restoration
Gate produces Vout “closer to rail”
Tolerates some drop between out and in
Call this our “Noise Margin”
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25. Noise Margin Voh – output high Vol – output low Vih – input high
Vil – input low
NMh = Voh-Vih
NMl = Vol-Vil
One mechanism,
addresses numerous
noise sources.
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26. Restoration Discipline
Define legal inputs
Gate works if Vin “close enough” to the rail
Vin > Vih or Vin < Vil
Restoration
Gate produces Vout “closer to rail”
Vout < Vol or Vout > Voh
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27. Restoring Transfer Function
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28. Restoring Transfer Function
For multi-input functions,
hold non-controlling inputs
at Vil, Vih respectively.
(relate preclass exercise)
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29. Ideal Transfer Function
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30. Linear Transfer Function?
O=Vdd-A
Noise Margin?
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31. Non-linearity Need non-linearity in transfer function
Could not have built restoring gates with
R, L, C circuit
Linear elements
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32. Transistor Non-Linearity
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33. All Gates If hope to assemble design from collection of gates,
Voltage levels must be consistent and supported across all gates
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34. Admin HW2 is out Monday in Ketterer Wednesday back here Lab combo
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35. Big Idea Need robust logic Restoration and noise margins
Can assemble into any (feed forward) graph
Can tolerate loss and noise
….while maintaining digital abstraction
Restoration and noise margins
Every gate makes signal “better”
Design level of noise tolerance
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