Interrupts 1/18/2019.

Interrupts 1/18/2019

Learning Objectives I Describe the interrupt process
Explain the difference between a nonmaskable and a maskable interrupt Explain the difference between a direct and a vectored interrupt List the priority of interrupt in 8085 List the 8085 vectored interrupts, nonmaskable interrupt and their vectored addresses 1/18/2019

What is an Interrupt ? A hardware interrupt is a CPU facility which permits spurious asynchronous events to suspend program execution and instead execute a software module to service the event. Interrupt is a process of data transfer where an external device can get the attention of the microprocessor. The process starts from the I/O device The process is asynchronous. (at any time) 1/18/2019

What is an Interrupt ? Interrupt pin :-
- connection to the processor which allows external devices to signal a request for service Interrupt service routine ( ISR ) :- - software module that the processor executes in response to an interrupt Interrupt mechanism :- - After completion of the ISR , the processor returns to execution of the main program from the point at which it was interrupted 4

Interrupt Event Sequence
1 normal processing 2 interrupt occurs 7 resume normal processing 3 save PC on stack 6 retrieve PC from stack 4 branch to ISR 5 execute ISR 5

Maskable and Non-maskable Interrupts
(Can be delayed or Rejected) If maskable interrupt is asserted, it will only interrupt the processor if it is enabled ( unmasked ). Maskable interrupts can be enabled ( unmasked ) or disabled ( masked ) by software. Most maskable interrupts automatically become disabled (masked) after an interrupt has occurred. It requires further software commands to re-enable maskable interrupts. 1/18/2019

Maskable and Non-maskable Interrupts
(CANNOT be delayed or Rejected) If a non-maskable interrupt is asserted, it will always interrupt the processor. The non-maskable interrupt is not affected by the value of the Interrupt Enable flip-flop. There is no software mechanism to prevent the processor being interrupted by a non-maskable interrupt. 1/18/2019 7

Direct and Vectored Interrupts
Direct interrupts The interrupting device need to provide the interrupt signal only. (i.e. to assert the signal to the interrupt pin of the processor.) The address of the subroutine is already known to the Microprocessor. The address of the first instruction of the ISR for the particular interrupt is pre-programmed into the CPU. 1/18/2019 8

Direct and Vectored Interrupts
Microprocessor requires external hardware to supply the address of the service routine. The interrupting device has to supply both the interrupt signal and the 16-bit address of the first instruction of the ISR. Interrupt service routines for vectored interrupts can reside anywhere in the memory map of the computer system. 1/18/2019 9

Interrupt Priority For processor with multiple interrupt input pins, the various interrupts are assigned a priority. When simultaneous interrupts occur, the highest priority interrupt will be serviced before lower priority interrupts. It is possible to arrange software such that whilst a lower priority interrupt is being serviced that a higher priority interrupt can interrupt the lower priority service routine. 1/18/2019

The 8085 Interrupts 8085 has 5 interrupt signals. (a) TRAP
INTA/ : interrupt acknowledgement signal (active low) (a) TRAP - Only non-maskable interrupt - It is direct interrupt (b) RST 7.5, RST 6.5, RST 6.5 - Direct interrupt - Maskable interruprt (c) INTR - Only vector interrupt - Maskable interrupt 8085 6 7 8 9 10 11 TRAP RST 7.5 RST 6.5 RST 5.5 INTR INTA/ 1/18/2019

8085A Interrupts Interrupt pins at 6, 7, 8, 9 and 10 for TRAP, RST 7.5, RST 6.5 and INTR respectively 12

The 8085 Interrupts Interrupt name Maskable Direct INTR Yes No RST 5.5
TRAP

The 8085 Interrupts 1/18/2019

Rising Edge AND High Level
Interrupt Trigger Type TRAP Rising Edge AND High Level RST 7.5 Rising Edge RST 6.5 High Level RST 5.5 INTR Notes : Rising Edge  Positive edge-triggered interrupt High Level  Level-triggered interrupt 15

Learning Objectives II
Describe the process of enabling and disabling the maskable, direct and vectored interrupts List the instructions related to interrupt process Explain the function of these instructions in the 8085 interrupt process 1/18/2019

Enabling and Disabling Maskable Interrupts
Maskable interrupts - RST 7.5, RST 6.5, RST 6.5, INTR - only interrupt the processor if it is enabled (unmasked) - Maskable interrupts can be enabled (unmasked) or disabled (masked) by software The individual masks for RST 5.5, RST 6.5 and RST 7.5 are manipulated using the SIM instruction This instruction takes the bit pattern in the Accumulator and applies it to the interrupt mask enabling and disabling the specific interrupts. 1/18/2019 17

Enabling and Disabling Maskable Interrupts
Instruction EI (Enable Interrupt) 1-byte instruction set the Interrupt Enable flip-flop and enables the interrupts process system reset or an interrupt disables after the interrupt process is done Instruction DI (Disable Interrupt) reset the Interrupt Enable flip-flop and disables the interrupts process

How SIM Interprets the Accumulator
SDO SDE XXX R7.5 MSE M7.5 M6.5 M5.5 1 2 3 4 5 6 7 Enable Serial Data 0 - Ignore bit 7 1 - Send bit 7 to SOD pin Serial Data Out Not Used RESET RST7.5 : If =1  RST 7.5 Flip Flop to reset OFF Mask Set Enable 0 - Ignore bits 0-2 1 - Set the masks according to bits 0-2 RST5.5 Mask RST6.5 Mask RST7.5 Mask } 0 – Available 1 - Masked 19

SIM and the Interrupt Mask
Bit 0 - mask for RST 5.5, bit 1 - mask for RST 6.5 and bit 2 - mask for RST 7.5 If the mask bit is 0, the interrupt is available. If the mask bit is 1, the interrupt is masked. Bit 3 (Mask Set Enable - MSE) is an enable for setting the mask. If it is set to 0 the mask is ignored and the old settings remain. If it is set to 1, the new setting are applied. The SIM instruction is used for multiple purposes and not only for setting interrupt masks. It is also used to control functionality such as Serial Data Transmission. Therefore, bit 3 is necessary to tell the microprocessor whether or not the interrupt masks should be modified

Using SIM instruction to Modify the Interrupt Mask
Example 1 : Set the interrupt masks so that RST 7.5 and RST 5.5 is enable and disable RST6.5 Determine the contents of the Accumulator Enable RST bit 0 = 0 Disable RST bit 1 = 1 SDO SDE XXX R7.5 MSE M7.5 M6.5 M5.5 Enable RST bit 2 = 0 Allow setting the masks bit 3 = 1 1 1 Don’t reset the flip flop bit 4 = 0 Bit 5 is not used bit 5 = 0 Don’t used serial data bit 6 = 0 Contents of accumulator are: 0AH Serial data is ignored bit 7 = 0 MVI A, 0A H SIM ;Set Interrupt Mask EI ;Enable Interrupt 21

Using SIM instruction to Modify the Interrupt Mask
Example 2 : Reset RST 7.5 interrupt from Example 1 Determine the contents of the Accumulator Enable RST bit 0 = 0 Disable RST bit 1 = 1 SDO SDE XXX R7.5 MSE M7.5 M6.5 M5.5 Enable RST bit 2 = 0 Allow setting the masks bit 3 = 1 1 1 1 Reset the flip flop bit 4 = 1 Bit 5 is not used bit 5 = 0 Don’t used serial data bit 6 = 0 Contents of accumulator are: 1AH Serial data is ignored bit 7 = 0 MVI A, 1A H SIM ;Set Interrupt Mask EI ;Enable Interrupt 22

Pending Interrupts Since the 8085 has five interrupt lines, interrupts may occur during an ISR and remain pending. Using the RIM instruction, it is possible to can read the status of the interrupt lines and find if there are any pending interrupts.

Reading The Status of Maskable Interrupts
RIM instruction :- - 1 byte instruction - To read the status of maskable interrupts. - This instruction loads the accumulator with 8-bits indicating the current status of the interrupt masks - to identify pending interrupts – Bit D4, D5 and D6 - to receive serial data – Bit D7 SDI P7.5 P6.5 P5.5 IE M7.5 M6.5 M5.5 1 2 3 4 5 6 7 RST5.5 Interrupt Pending RST6.5 Interrupt Pending RST7.5 Interrupt Pending } 1 - Pending Serial Data In Interrupt Enable Value of the Interrupt Enable Flip Flop [1 – Enable] RST5.5 Mask RST6.5 Mask RST7.5 Mask } 0 - Available 1 - Masked 24

Instructions in Interrupt Process
When a device interrupts, it actually wants the MP to call a subroutine  Interrupt Service Routine (ISR) EI (Enable Interrupts) instruction 1-byte instruction Sets the Interrupt Enable flip-flop and enables the interrupt process. System reset or an interrupt disables after the interrupt process is done. enables the vectored interrupt INTR and the restart interrupts RST 5.5, RST 6.5 and RST 7.5. DI (Disable Interrupts) instruction 1-byte instruction Resets the Interrupt Enable flip-flop and disables the interrupt process. disables all maskable interrupts. Should be included in a program segment where an interrupt from an outside source cannot be tolerated. 1/18/2019 25

Direct Interrupts [ TRAP, RST 5.5, RST 6.5, RST 7.5 ]
BI-bus idle, MW- memory Write 26

The 8085 Maskable/Direct Interrupts
The 8085 has 3 Masked/Direct interrupt inputs. RST 5.5, RST 6.5, RST 7.5 They are all maskable. They are automatically direct according to the following table: The vectors for these interrupt fall in between the vectors for the RST instructions. That’s why they have names like RST 5.5 (RST 5 and a half). Interrupt Vector RST 5.5 002CH RST 6.5 0034H RST 7.5 003CH

Masking RST 5.5, RST 6.5 and RST 7.5 These three interrupts are masked at two levels: Through the Interrupt Enable flip flop and the EI/DI instructions. The Interrupt Enable flip flop controls the whole maskable interrupt process. Through individual mask flip flops that control the availability of the individual interrupts. These flip flops control the interrupts individually.

Maskable Interrupts and vector locations
RST7.5 Memory RST 7.5 M 7.5 RST 6.5 M 6.5 RST 5.5 M 5.5 INTR ** See Fig 12.5 of the Text Book for a detailed look Interrupt Enable Flip Flop

The 8085 Maskable/Direct Interrupt Process
The interrupt process should be enabled using the EI instruction. The 8085 checks for an interrupt during the execution of every instruction. If there is an interrupt, AND if the interrupt is enabled using the interrupt mask, the microprocessor will complete the executing instruction, and reset the interrupt flip flop. The microprocessor then executes a call instruction that sends the execution to the appropriate location in the interrupt vector table.

The 8085 Maskable/Direct Interrupt Process
When the microprocessor executes the call instruction, it saves the address of the next instruction on the stack. The microprocessor jumps to the specific service routine. The service routine must include the instruction EI to re-enable the interrupt process. At the end of the service routine, the RET instruction returns the execution to where the program was interrupted.

Machine Cycles with Direct Interrupts
Since there is no requirement to supply ISR addresses with direct interrupts ( TRAP, RST 5.5, RST 6.5 & RST 7.5 ), then there is no requirement for the 8085A to execute INTA machine cycles in response to such interrupts. However to provide the CPU sufficient time to process a direct interrupt a six T-state bus idle machine cycle is introduced, following recognition of the direct interrupt. During the bus idle machine cycle NO control signal is asserted NOR is the program counter incremented. Ready line control is ignored during the bus idle cycle. Following the bus idle cycle two memory write cycles are executed to save the current contents of the program counter on the stack. The program counter is then overwritten with the pre-programmed address for the particular interrupt source. 1/18/2019 32

Normal operation cycles BI-bus idle, MW- memory Write * No INTA machine cycle – Direct Interrupt Since there is no requirement to supply ISR addresses with direct interrupts ( TRAP, RST 5.5, RST 6.5 & RST 7.5 ) then there is no requirement for the 8085A to execute INTA machine cycles in response to such interrupts. 33

BI-bus idle, MW- memory Write * No INTA machine cycle – Direct Interrupt However to provide the CPU sufficient time to process direct interrupt - six T-state bus idle machine cycle is introduced, following recognition of the direct interrupt. 34

BI-bus idle, MW- memory Write * No INTA machine cycle – Direct Interrupt During the bus idle machine cycle, NO control signal is asserted NOR is the program counter incremented. Ready line control is ignored during the bus idle cycle. 35

BI-bus idle, MW- memory Write * No INTA machine cycle – Direct Interrupt Following with the bus idle cycle which is two memory write cycles are executed to save the current contents of the program counter on the stack. 36

BI-bus idle, MW- memory Write * No INTA machine cycle – Direct Interrupt The program counter is then overwritten with the pre-programmed address for the particular interrupt source. 37

Vector Interrupts [ INTR ]
BI-bus idle, MW- memory Write 38

Vector Interrupts (INTR)
INTR is a vector interrupt and it is also maskable interrupt The interrupt process - enabled using EI instruction. RST instruction - used to transfer the program control to specific memory location. The 8085 recognizes 8 RST (Restart) instructions. RST n, where 0 ≤ n ≤ 7 ((SP) - 1)  (PCH) ((SP) - 2)  (PCL) ((SP)  (SP) – 2 (PC)  8 * n 1/18/2019 39

RST n RST n In respond to the INTA/ strobe, external logic places an RST n opcode on the data bus. RST n has the following bit pattern; 11NNN111 where; n = NNN (3 bit binary number) restart address is n * 8 For example if:- RST 1, NNN = 001 and restart address is 08H. (= 001*8) RST 2 (address 10H), RST 3 (address 18H) and etc. 1/18/2019 40

RST n RST n RST n 1 1 N N N 1 1 1 Mnemonic Binary Code Hex Code
Call Location in Hex D7 D6 D5 D4 D3 D2 D1 D0 RST 0 1 C7 0000 RST 1 CF 0008 RST 2 0010 RST 3 DF 0018 RST 4 E7 0020 RST 5 EF 0028 RST 6 F7 0030 RST 7 FF 0038 RST n 1/18/2019 N N N 41

Each of these instructions would send the execution to a predetermined hard-wired memory location:
ORG 0000H JMP START ORG 0028H JMP VRST5 ORG 0030H JMP VRST6 START: …. EI ….. VRST5: ….. RET VRST6: ….. Restart Instruction Equivalent to RST 0 CALL 0000H RST 1 CALL 0008H RST 2 CALL 0010H RST 3 CALL 0018H RST 4 CALL 0020H RST 5 CALL 0028H RST 6 CALL 0030H RST 7 CALL 0038H 1/18/2019 42

The 8085 Vectored Interrupt Process
Interrupt Enable Process The interrupt process should be enabled by writing the EI instruction in the main program. INTR line checking The 8085 checks for an interrupt (INTR line) during the execution of every instruction. Interrupt Acknowledgement If INTR is high, Interrupt (EI) is enabled: MP completes current instruction Disables the Interrupt Enable flip-flop Sends INTA/ (Interrupt acknowledge) signal to the device that interrupted MP cannot except any interrupt request until the interrupt flip-flop is enabled again.

Interrupt Acknowledgement INTA/ allows the I/O device to send a RST instruction through data bus. RST (Restart) instruction 1-byte instruction Transfer the program control to a specific memory location on page 00H Restarts the execution at that memory location after executing Step 5.

Save PC on stack Upon MP receiving the INTA/ signal: MP saves the memory address of the next instruction cycle on the stack. The program is transferred to ‘CALL’ location (ISR Call) specified by the RST instruction ISR Execution Assuming that the task to be performed is written as a subroutine at specified location, MP performs the task (ISR).

Include EI in ISR ISR must include the ‘EI’ instruction to enable the next interrupt within the program. Retrieve PC from stack RET instruction at the end of the ISR allows the MP to retrieve the return address from the stack. The program is transferred back to where the program was interrupted. MP continues the execution.

Machine Cycles with Vectored Interrupts
The 8085A processor executes a number of machine cycles, in response to a vectored interrupt (INTR), prior to execution of the first instruction of the interrupt service routine. The processor completes the execution of the current instruction. (Note : The processor only samples the interrupt inputs in the last T-state of the last machine cycle in the current instruction cycle) This has implication in system design as it means that the interrupt signal on INTR must remain in the asserted state for at least the longest instruction in the 8085A instruction set to guarantee that the processor recognizes the interrupt. 1/18/2019

The processor then executes a six T-state interrupt acknowledge machine cycle ( the INTA machine cycle is similar to the opcode fetch machine cycle except that the program counter is not incremented and the INTA/ control signal is asserted instead of RD/) In response to the INTA/ signal, the interrupting device need to place the opcode of an instruction onto the data bus ( called jamming ). The processor reads the opcode in the normal manner and stores it in the instruction register. The choice of opcode is restricted as it is necessary to automatically save the contents of the program counter to enable the program to return to the point in the software where it was interrupted. 1/18/2019

Machine Cycles with Vectored Interrupts (CALL)
The only viable choice of 8085A instruction is either the CALL instruction or the RST n instruction. The CALL instruction is a 3-byte instruction with bytes 2 & 3 being the address of the first instruction of the subroutine ( in this case the interrupt service routine). Following decoding of the call opcode, the processor executes a further two interrupt acknowledge machine cycles to fetch the address of the start of the ISR. It is incumbent on the interrupting device to place the low byte of the address of the ISR onto the data bus in response to the second INTA/ control signal and the high byte of the address in response to the third INTA/ signal. 1/18/2019

Machine Cycles with Vectored Interrupts (CALL)
The execution phase of the CALL instruction can now take place. The processor firstly executes two memory write machine cycles to save the current contents of the program counter onto the stack. The address as to where in memory the contents of PC is to be saved is specified by the stack pointer register. Finally the processor overwrites the contents of the program counter with the second and third bytes of the call instruction. The next instruction the processor will execute will be the first instruction of the ISR. 1/18/2019

The processor then executes a six T-state interrupt acknowledge machine cycle ( the INTA machine cycle is similar to the opcode fetch machine cycle except that the program counter is not incremented and the INTA/ control signal is asserted instead of RD*) 51

In response to the INTA/ signal, the interrupting device need to place the opcode of an instruction onto the data bus ( called jamming ). The processor reads the opcode in the normal manner and stores it in the instruction register. 52

The choice of opcode is restricted as it is necessary to automatically save the contents of the program counter to enable the program to return to the point in the software where it was interrupted. 53

The only viable choice of 8085A instruction is either the CALL instruction or the RST n instruction. The CALL instruction is a 3-byte instruction with bytes 2 & 3 being the address of the first instruction of the subroutine ( in this case the interrupt service routine). 54

Following decoding of the call opcode, the processor executes a further two interrupt acknowledge machine cycles to fetch the address of the start of the ISR. 55

Low Byte in 2nd INTA It is incumbent on the interrupting device to place the low byte of the address of the ISR onto the data bus in response to the second INTA/ control signal and the high byte of the address in response to the third INTA/ signal. 56

High Byte in 3rd INTA It is incumbent on the interrupting device to place the low byte of the address of the ISR onto the data bus in response to the second INTA/ control signal and the high byte of the address in response to the third INTA/ signal. The execution phase of the CALL instruction can now take place. 57

The execution phase of the CALL instruction can now take place. The processor firstly executes two memory write machine cycles to save the current contents of the program counter onto the stack. The address as to where in memory the contents of PC is to be saved is specified by the stack pointer register. 58

Finally the processor overwrites the contents of the program counter with the second and third bytes of the call instruction. The next instruction the processor will execute will be the first instruction of the ISR. 59

The 8085 Interrupts Interrupt Name Maskable Masking Method Direct/
Vectored Memory Triggering Method INTR Yes DI / EI No Level Sensitive RST 5.5 / RST 6.5 SIM Direct RST 7.5 Edge Sensitive TRAP None Level & Edge Sensitive

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