1. Post-Silicon Calibration for Large-Volume Products
Edward Kao and Scott Fukushima

2. Outline Self-Calibration Method for D/A Converters
Frequency Calibration
Post-Silicon-Tunable Clock-Tree Synthesis
Path-Based Learning
Adaptive Body Bias Clustering
Summary of Papers
Paper Comparisons

3. Self Calibration Method for D/A Converters

4. A Self-Calibration Method for tuning DAC’s
Problem Statement
Transistor mismatches of signal current sources cause non-linearity of DAC transfer characteristics
Existing work done in externally tuned DACs but without a fully integrated self-calibration approach that works at high frequencies as solved in this research
Proposed Solution
A self-calibrating circuit that only needs to be tuned once and enhances the linearity of the circuit
Assumption: current mismatch is a static error, and therefore the calibration routine needs to be executed only once at chip power up. This gives a significant improvement at higher frequencies over the dynamically calibrated techniques

5. Tuning Circuitry 1 bit comparator
Elements
1 bit comparator
A tunable temporary current source Itemp
A reference current source Ibinref
Tunable current sources to be used in the DAC Ith(i)
Switches to select between current sources to tune

6. FSM Algorithm

7. Key Results
Sweep through all digital codes shows Integral nonlinear error decreases significantly between the non-calibrated measurement vs. the self-calibrated measurement
In comparison with other works, the SFDR is very good while only needing 12 bits to achieve comparable accuracy which gives credit to the frequency independent tuning

8. Frequency Calibration

9. Freq. Calibration (Motivation)
Speed-binning
Process variation can lead to 30% speed variation
Classification of voltage-frequency (V-Fmax) based on chip speed for different purposes
Requires method to find chip max frequency
Voltage supply
Temperature

10. Freq. Calibration (Old Methods)
Finding max frequency at various operating voltages
Critical-path replica to estimate post-manufacture critical path delay
Does not account for process variation
Delay measurement hardware on manufactured chip
Lots of overhead for delay sensors
Needs high-speed clock or on-chip reference voltages

11. Freq. Calibration (New Method)
Requires conventional calibration at nominal voltage
Choose paths with highest critical timing and voltage sensitivity using equations and simulation
Voltage sensitivity is the path delay’s vulnerability to a voltage shift
Add ring oscillator and measure frequency to find measured voltage sensitivity
Use voltage sensitivity and critical delay to estimate max frequency at other voltages

12. Freq. Calibration (Results)
Accuracy Results

13. Freq. Calibration (Results)
Overhead

14. Statistical Timing Analysis Driven Post-Silicon Tunable Clock Tree Synthesis

15. Statistical Timing Analysis Driven Post-Silicon Tunable Clock-Tree Synthesis
Problem Statement
Process variation causes problems for yield
Functional – Stuck at faults, bridge faults etc.
Timing – Setup and Hold time violations
Circuits failing timing can often be fixed by adjusting the slack in the circuit through the use of tunable clock buffers
Tunable clock buffers add cost to the circuit in terms of area, so a method is needed to determine where to place the tunable clock buffers and the tunable range
Up to this point, there hasn’t been a generic strategic method for solving this problem for any type of design
Proposed Solution
Develop a strategic method for determining tunable range of clock buffers, and which clock buffers to make tunable to meet yield requirements while minimize area

16. Strategic Steps Create the Slack Vector Perform Slack Filtering
Hold Time Slack = Skewi,j + mindelayi,j - Holdj
Setup Time Slack = Period – maxdelayij – skewij - setupj
Create slack vector S that contains slack for each path
Express the slack vector as a Gaussian Distribution to add randomness into the simulations S ~ N(µs,∑s)
Perform Slack Filtering
Create a threshold for which enough slack is enough to not be concerned with and remove these rows from the slack vector
Create a Timing Yield Model:

17. Strategic Steps (continued)
Narrow down the possible tunable buffer candidates. Simply remove the clock buffers that are attached to paths that were declared to have enough slack previously
Determine the tunable ranges for each buffer
Problem formulated using the equation
An iterative simultaneous perturbation algorithm is used to solve this equation.
Algorithm iterates through various values of the tunable ranges, ri, and continually takes the gradient. After having the set of gradients, it takes the set of tunable ranges that gives the maximum value.

18. Strategic Steps (continued)
Final step is to narrow down the number of tunable buffers while maintaining the desired yield.
Batch selection algorithm as shown below is used

19. Results

20. Path-Based Learning

21. Path-Based Learning (Introduction)
Use path-based learning to extract a set of critical paths
Assume test chips available (either manufactured or from statistical timing simulator)
Use chip pass/fail behavior based on pattern sets with feature path selection
Use of SVM (Support Vector Machine) learning engine to handle large inputs

22. Path-based Learning (Algorithm)
Feature Path Selection

23. Path-based Learning (Conclusion)
Initial UR path set size of 6932, reduced UR path set size is 377 at STA clock = 150 for equal error
Does not give complete post-silicon validation and methodology
Only used as first step to filter out paths
Need more sophisticated methods to analyze the selected paths

24. A Statistical Framework for Post-Silicon Tuning through Body Bias Clustering
Problem Statement
Process variation causes transistors to have varying delay and power consumption. To make the die meet the power and delay constraints, we can perform adaptive body biasing.
Proposed Solution
Adaptive body biasing is well established. Previous works were done to determine the body voltages, but had fixed body voltages at design time, not giving the post-silicon calibration option. Other works had ABB for individual device wells post-silicon
This is the first work to generate a scalable clustering approach to reduce the number of ABB control voltages and overhead to practical levels

25. Background
Forward biasing the source-body voltage reduces the threshold voltage to increase speed while increasing leakage
Reverse biasing the source-body voltage reduces the threshold voltage to reduce speed while saving power
One can alter the threshold voltage to meet the desired timing and power constraints

26. Algorithm Overview
Create equations relating delay, power, biasing, and channel length throughout the circuit
Introduce random variables for channel length and simulate several solutions to create PDFs for each gate
Cluster the gates according to their PDFs
In the example below, gates 2, 5, 6, and 7 would make a good cluster since they are strongly correlated and also have similar mean and variances

27. Results

28. Results (continued)

29. Summary of Papers Self Calibration of a D/A Converter
Circuitry proposed to automatically match the current sources in the DAC to a reference current
Results showed significant improvement in the measured output in comparison to the correct output
Frequency Calibration
Method developed to efficiently find the voltage-frequency relationship of the chip
Method used to approximate the maximum frequency at different operating voltages
Post Silicon Tunable Clock-Tree Synthesis
Algorithm developed to efficiently determine the tuning range for each tunable clock buffer, and where to place the tunable clock buffers
Goal is to meet yield requirements while minimizing area
Path Finding
Reduce number of critical paths to analyze during post-silicon debug
Adaptive Body Bias Clustering Technique
Method developed to cluster the gates to minimize the number of clusters needed to optimize the power and delay of the circuit

30. Comparisons
All post-silicon tuning papers address problems due to process variations
Time of Optimization
Design-time optimization to remove post-silicon step
DAC self-calibration
Combined design-time and post-silicon optimization
Tunable Clock Tree, Body Bias Clustering, Frequency Calibration
Optimization Goals
Test Time
DAC self-calibration, Frequency calibration, Path-based learning
Area Improvement
DAC self-calibration, Tunable clock-tree, Body bias clustering 30

31. Thank you !