1. Combinational Circuit Design
Chapter 6
Combinational Circuit Design

2. Compound Gates

3. Asymmetric Gates To optimize for the input-to-output delay
Cap on the input A is (2+4/3)=10/3
Logical effort=(10/3)/3=10/9
Better than Normal NAND gates (4/3)
To optimize for the input-to-output delay

4. Pseudo-nMOS works well for wide NOR structures than NAND structures
HW. 6.19

5. Cascade Voltage Switch Logic (CSVL)
Advantages:
1. Without the static power consumption
2. Due to logic with nMOS, the speed can be
improved
3. The input capacitance is reduced
4. Require the complement logic
HW. 6.26

6. Dynamic Circuits

7. To ovoid error contention during precharge phase
Footed and Unfooted DG
To ovoid error contention during precharge phase

8. Dynamic Gates Advantages: 1.Zero static power consumption
2. Fastest circuit family
Disadvantages:
Require Clocking
Consume dynamic power consumption
3. Sensitive to noise

9. Problems of Dynamic Gates

10. Inherent non-inverting
Domino Gates
Inherent non-inverting

11. DG suffers from charge leakage on the dynamic node.
Keepers
DG suffers from charge leakage on the dynamic node.
Keeper is a weak MOS that holds the output at the correct level when it floats.

12. Charge Sharing of DG

13. NP Domino Gates

14. Pass-Transistor Circuits

15. CMOS TG

16. Threshold Drops

17. Ratio Failures
Weak transistor must be sufficiently small that the output level falls below VIL
of the next stage

18. Charge Sharing

19. Power Supply Noise
IR drop and di/dt noise cause noise margin problems and degrade delay margins

20. Back-gate Coupling
Resulting in a droop on the dynamic node X

21. Sense Amplifier