1. Data path for Multi-Cycle Processor Design2 M m o r y D a W d u x 1 I n s c [ 5 – ] 4 g 3 6 A L U Z B R P C O p - J 8
ALU E
Add
zeros

2. Finite State Machine Graph for Control Unit= 1 B O p P C W i t e o n d u R g D s M m I a f h / J l E x y - b k ( ' ) Q 4 9 8 6 2 7 5 3
ALUSrcA=0
ALUSrcB=01
ALUOp=01

3. Truth Table for ALU Control Unit
Ainvert Bivert Operation
ALUOp
Funct field
ALU
Control
ALUOp1
ALUOp0 F5 F4 F3 F2 F1 F0 d
0 0 10 1
0 1 10
0 0 00
0 0 01
0 1 11
add
sub
and or
slt
nor
Input Output
1 1 00
g. babic