1. A Fully Physical Model for Leakage Distribution under Process Variations in Nanoscale Double-Gate CMOS
Liu Cao
Lin Li

2. Outline Introduction Nanoscale Double-Gate Background
Double-Gate Leakage Model
Leakage Distribution
Multiple-Device Stacks

3. Introduction
Multi-gate technologies are the forerunners to replace bulk CMOS.

4. Why multi-gate is better?
Thicker gate insulator
Superior short channel characteristics
Improved mobility in the undoped body
Elimination of random dopant effects

5. Double-Gate vs Bulk

6. Process Variation in Circuit Design

7. Which model should we use?
Compact SPICE-like models [3, 2]?
Analytical Model: Semi-physical Vth [11, 4, 5]?
Physical and Analytical Model: This paper.

8. Contribution of this paper
Derive a fully physical model for double-gate leakage
Develop a model for single device leakage distribution due to gate length and body thickness variations
Extend the model to multiple-device stacks

9. Outline Introduction Nanoscale Double-Gate Background
Double-Gate Leakage Model
Leakage Distribution
Multiple-Device Stacks

10. Ideal Double-Gate MOSFET Structure

11. Physical Model of this paper
In this paper, only symmetric tox , VGS and ∆ΦMS model is considered

12. Short Channel Effect (SCE)
The 2-D potential distribution is derived as a solution of Poisson’s equation [9].

13. Quantum Confinement Effect (QCE)
QCE leads to quantization of energy levels, and finite probability of occupation of these levels
Both the wave functions and quantized energy levels are solutions of the 1-D Schrodinger’s equation.

14. Process Variations tox and ∆ΦMS are maintained the nominal values.
L and t have variations.

15. Outline Introduction Nanoscale Double-Gate Background
Double-Gate Leakage Model
Leakage Distribution
Multiple-Device Stacks

16. Subthreshold Diffusion Current
In which nc (x, y) represents the effective carrier concentration:

17. SCE – Electrostatic potential a [9]
Poisson’s Equation:
With the boundary conditions

18. Derivation for a
Using superposition, the electrostatic potential in DG can be written as:
Where vxx is the 1-D solution to equation
Sssssssssssss are the solutions to
satisfy the top and bottom boundary conditions

19. Dielectric Boundary Conditions
Take ratios of these equations and get the Eigen Value Equation

20. Fully potential expression in Subthreshld region

21. Derivation for Subthreshold current
The current density can be written as:
Integrating in x and z directions gives:
Where
Is the inversion charge per gate area.

22. Final Subthreshold current [9]
Current continuity requires Ids be independent of y.

23. QCE – intrinsic carrier concentration [13]
It is calculated from the density of states, and the probability of occupation based on the D wavefunction solution.

24. Compact Solution for Leakage Current
KEY:
Isub can be captured by accounting for the potential at the center of the ultra-thin body (x=0), and at the top of the source-drain barrier (y=ytop).

25. Verification for the Analytical Model
Worst case (WC) means highest leakage
Best case (BC) means lowest leakage

26. Outline Introduction Nanoscale Double-Gate Background
Double-Gate Leakage Model
Leakage Distribution
Multiple-Device Stacks

27. Leakage distribution
Expand as 2-D Taylor series

28. Leakage distribution(cont.)
is the i-th partial derivative of
with respect to L

29. Leakage distribution(cont.)
Thus, we have:
where
and
The expectation of this random variable can be calculated as:

30. Leakage distribution(cont.)
 kth central moment of a real-valued random variable X is the quantity μk := E[(X − E[X])k], where E is the expectation operator. For a continuous univariate probability distribution with probability density function f(x) the moment about the mean μ is

31. Leakage distribution(cont.)
Assuming independent distribution, if L and tsi are distributed normally, then their central moments can be evaluated as:
the variance of

32. Leakage distribution(cont.)

33. 1.4

34. Outline Introduction Nanoscale Double-Gate Background
Double-Gate Leakage Model
Leakage Distribution
Multiple-Device Stacks

35. Multiple-Device Stacks1

36. Multiple-Device Stacks(cont.)
Expand as 3-D Taylor Series

37. Multiple-Device Stacks(cont.)

38. Multiple-Device Stacks(cont.)

40. Reference
[7] Q. Chen, E. M. Harrell, and J. D. Meindl. A physical short- channel threshold voltage model for undoped symmetric double- gate MOSFETs. IEEE Trans.Electron Devices, 50(7):1631–1637, Jul
[9] X. Liang and Y. Taur. A 2-D analytical solution for SCEs in DG MOSFETs. IEEE Trans. Electron Devices, 51(8):1385–1391, Aug
[11] R. Rao, A. Srivastava, D. Blaauw, and D. Sylvester. Statistical analysis of subthreshold leakage current for VLSI circuits. IEEE Trans. VLSI, 12(2):131–139, Feb 2004.
[13] V. P. Trivedi and J. G. Fossum. Quantum-mechanical effects on the threshold voltage of undoped double-gate MOSFETs. IEEE Electron Device Lett., 26(8):579–582, Aug 2005.
[14] S. Xiong and J. Bokor. Sensitivity of double-gate and FinFET devices to process variations. IEEE Trans. Electron Devices, 50(11):2255–2261, Nov 2003.