1. ultraSPARC과 SIC/XE Machine 비교
( 219 )
컴퓨터학부 박 연 호

2. ultraSPARC Architecture
ultraSPARC architecture is designed to be a target for optimizing compilers and high-performance hardware implementations.
ultraSPARC architecture allows for a spectrum of processor and system implementations at a variety of price/applications, including scientific/engineering, programming, real-time, and commercial apllications.

3. Memory SIC/XE Machine ultraSPARC Structure 1 byte – 8 bit
1 word – 3 byte
All address on SIC/XE are byte address
Words are addressed by lowest numbered byte
Max memory size – 1 Mbyte (220bytes)
ultraSPARC
1 word – 4 byte
All address on ultraSPARC are byte Address
Use Big-endian and Little endian
Max memory size – 264 bytes virtual memory

4. Register SIC/XE Machine ultraSPARC 9 registers Register name
All have their own special purpose
24-bit length
Register name
A (Accumulator), X (Index), L (Linkage), PC (Program Counter), SW (Status Word)
B (BaseRegister), S, (General register) T (General register), F (Floating register)
ultraSPARC
More than 100 registers
32-bit length
Only 32 registers can use for User
r0~r7 is global register, other 24 register use register file
64 double-precision floating-point register

5. Data Format - 1 SIC/XE Machine Integer : 24-bit binary number
2’s complement representation
-223 ~
Character : 8-bit ASCII code
Floating-point : 48-bit floating-point data type
S: sign of fraction (0=positive, 1=negative)
Fraction: the high-order bit of the fraction must be 1
Exponent: unsigned binary number (0 ~ 2047)
Absolute value = fraction * 2(exp )

6. Data Format - 2 ultraSPARC Integer : 8-,16-,32-.64-bit binary number
Character : 8-bit ASCII code

7. Data Format - 3 <- 32bit 64bit -> <- 128bit
Floating-point : 32-,64-,128-bit binary number
<- 32bit
64bit ->
<- 128bit

8. Instruction Format - 1
SIC/XE Machine

9. Instruction Format - 2 ultraSPARC
All instruction on SPARC have 32bit format
SPARC have three basic Format
First two bit determine format

10. Addressing Modes - 1 SIC/XE Machine Use relative addressing Extend the
address field
to 20 bits

11. Addressing Modes - 2
ultraSPARC
Immediate mode
Register direct mode

12. Instruction Set - 1 SIC/XE Machine ultraSPARC
Load & Store : LDA, LDX, LDL, LDCH, STA, STX, STL, STCH, STSW
Arithmetic & Logical : ADD, ADDR, SUB, SUBR, MUL, DIV, AND, OR, TIX
Compare : COMP
Control : J, JLT, JEQ, JGT
I/O : SIO, TIO, HIO
ultraSPARC
Load & Store : LDD, LDDA, LDDF, LDDFA, LDSH, STB, STBA, STD, STDF, STW
Arithmetic & Logical : ADD, ADDC, AND, ANDN, FDIV, FMUL, AND, ANDN, OR, ORN…
Compare : CASA, CASXA, FCMP
Control : JMPL
I/O : Not operator. Using load, store operator access TSB

13. Instruction Set - 2

14. Instruction Set - 3

15. Instruction Set - 4

16. Instruction Set - 5

17. Instruction Set - 6

18. Instruction Set - 9

19. 감사 합니다.
자료출처 : ultraSPARC Architecture 2005 PDF