1. Topic 6: Pipelining and Pipelined Architecture
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2. Reading List Slides: Topic6x Henn & Patt: Chapter 6
Other papers as assigned in class or homeworks
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3. Pipelining What is pipelining - basic concepts
Pipelined datapath: A case study of MIPS
Pipeline control
Pipeline hazard resolution
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4. Pipelining – the basic concepts
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5. Basic Concept
Pipeline: multiple instructions are simultaneously in execution
Pipeline is divided into “segments” or “stages”
Machine cycle:
Time required to move through one stage
Machine cycle is determined by the slowest stage in the pipe
Often
Machine Clock
cycle cycle =
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6. In a perfectly balanced pipelined machine instruction time =
In a normal machine
(1) is not true,
i.e. - stage time does not equal there is
overhead
but it can be very close to 10% within (1)
non-pipe time
# of pipe stages
(1)
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7. Pipelining as an Architecture Technique
Generally may be invisible to user
Scalar pipelined machine vs. vector machine
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8. # of instructions cycle completed Pipeline throughout
So pipeline increases throughout, but the time for execution of each instruction remains unchanged.
Clock rate of a pipelined machine is limited by:
latch time
clock skew
the delay time required for clock signals to propagate on a chip.
# of instructions
completed
cycle
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9. Performance Limitations of a Pipeline
Rate cannot exceed the slowest stage
Complexities in reality
- different processing time for different stages
- interaction/dependencies between stages - may be data dependent (dynamic)
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10. The most important factors on “pipe beat” (cycle time)
STAGE 1 LACHES
Combinational Logic
STAGE 2 LACHES
STAGE 3 LACHES
STAGE n LACHES
(b)
The most important factors on “pipe beat” (cycle time)
latch delay and clock skew
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11. Overlap vs. Pipeline Pipeline: tightly coupled subfunctions
fixed basic stage time
independent basic function evaluation
Overlap
Loosely coupled subfunctions
variable basic stage time
dependency between function evaluation
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12. CPU/I/O Overlapping Common memory Computational processor (stage 1)
Input/output
processor
(stage 2)
1 Task Task Task Task
2 Task Task Task Task 1
Time =Idle time
CPU/I/O Overlapping
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13. MIPS Pipeline Pipeline stages: IF ID (decode + Reg fetch) EX MEM
Write back
On each clock cycle another instruction is fetched and begins its five-step execution. If an
instruction is started every clock cycle, the performance will be five times that of a machine
that is not pipelined.
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14. MIPS Pipeline - Another Representation
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