1. William Stallings Computer Organization and Architecture 8th Edition
Chapter 15
Control Unit Operation

2. A computer executes a program Fetch/execute cycle
Micro-Operations
A computer executes a program
Fetch/execute cycle
Each cycle has a number of steps
see pipelining
Called micro-operations
Each step does very little
Atomic operation of CPU

3. Constituent Elements of Program Execution

4. Memory Address Register (MAR)
Fetch - 4 Registers
Memory Address Register (MAR)
Connected to address bus
Specifies address for read or write op
Memory Buffer Register (MBR)
Connected to data bus
Holds data to write or last data read
Program Counter (PC)
Holds address of next instruction to be fetched
Instruction Register (IR)
Holds last instruction fetched

5. Fetch Sequence
Address of next instruction is in PC
Address (MAR) is placed on address bus
Control unit issues READ command
Result (data from memory) appears on data bus
Data from data bus copied into MBR
PC incremented by 1 (in parallel with data fetch from memory)
Data (instruction) moved from MBR to IR
MBR is now free for further data fetches

6. Fetch Sequence (symbolic)
t1: MAR <- (PC)
t2: MBR <- (memory)
PC <- (PC) +1
t3: IR <- (MBR)
(tx = time unit/clock cycle) or
t3: PC <- (PC) +1
IR <- (MBR)

7. Rules for Clock Cycle Grouping
Proper sequence must be followed
MAR <- (PC) must precede MBR <- (memory)
Conflicts must be avoided
Must not read & write same register at same time
MBR <- (memory) & IR <- (MBR) must not be in same cycle
Also: PC <- (PC) +1 involves addition
Use ALU
May need additional micro-operations

8. Indirect Cycle
MAR <- (IRaddress) - address field of IR
MBR <- (memory)
IRaddress <- (MBRaddress)
MBR contains an address
IR is now in same state as if direct addressing had been used
(What does this say about IR size?)

9. t2: MAR <- save-address PC <- routine-address
Interrupt Cycle
t1: MBR <-(PC)
t2: MAR <- save-address
PC <- routine-address
t3: memory <- (MBR)
This is a minimum
May be additional micro-ops to get addresses
N.B. saving context is done by interrupt handler routine, not micro-ops

10. Execute Cycle (ADD)
Different for each instruction
e.g. ADD R1,X - add the contents of location X to Register 1 , result in R1
t1: MAR <- (IRaddress)
t2: MBR <- (memory)
t3: R1 <- R1 + (MBR)
Note no overlap of micro-operations

11. ISZ X - increment and skip if zero
Execute Cycle (ISZ)
ISZ X - increment and skip if zero
t1: MAR <- (IRaddress)
t2: MBR <- (memory)
t3: MBR <- (MBR) + 1
t4: memory <- (MBR)
if (MBR) == 0 then PC <- (PC) + 1
Notes:
if is a single micro-operation
Micro-operations done during t4

12. BSA X - Branch and save address
Execute Cycle (BSA)
BSA X - Branch and save address
Address of instruction following BSA is saved in X
Execution continues from X+1
t1: MAR <- (IRaddress)
MBR <- (PC)
t2: PC <- (IRaddress)
memory <- (MBR)
t3: PC <- (PC) + 1

13. Each phase decomposed into sequence of elementary micro-operations
Instruction Cycle
Each phase decomposed into sequence of elementary micro-operations
E.g. fetch, indirect, and interrupt cycles
Execute cycle
One sequence of micro-operations for each opcode
Need to tie sequences together
Assume new 2-bit register
Instruction cycle code (ICC) designates which part of cycle processor is in
00: Fetch
01: Indirect
10: Execute
11: Interrupt

14. Flowchart for Instruction Cycle

15. Functional Requirements
Define basic elements of processor
Describe micro-operations processor performs
Determine functions control unit must perform

16. Basic Elements of Processor
ALU
Registers
Internal data pahs
External data paths
Control Unit

17. Types of Micro-operation
Transfer data between registers
Transfer data from register to external
Transfer data from external to register
Perform arithmetic or logical ops

18. Functions of Control Unit
Sequencing
Causing the CPU to step through a series of micro-operations
Execution
Causing the performance of each micro-op
This is done using Control Signals

19. Control Signals Clock Instruction register Flags From control bus
One micro-instruction (or set of parallel micro-instructions) per clock cycle
Instruction register
Op-code for current instruction
Determines which micro-instructions are performed
Flags
State of CPU
Results of previous operations
From control bus
Interrupts
Acknowledgements

20. Model of Control Unit

21. Control Signals - output
Within CPU
Cause data movement
Activate specific functions
Via control bus
To memory
To I/O modules

22. Example Control Signal Sequence - Fetch
MAR <- (PC)
Control unit activates signal to open gates between PC and MAR
MBR <- (memory)
Open gates between MAR and address bus
Memory read control signal
Open gates between data bus and MBR

23. Data Paths and Control Signals

24. Internal Organization
Usually a single internal bus
Gates control movement of data onto and off the bus
Control signals control data transfer to and from external systems bus
Temporary registers needed for proper operation of ALU

25. CPU with Internal Bus

26. Hardwired Implementation (1)
Control unit inputs
Flags and control bus
Each bit means something
Instruction register
Op-code causes different control signals for each different instruction
Unique logic for each op-code
Decoder takes encoded input and produces single output
n binary inputs and 2n outputs

27. Hardwired Implementation (2)
Clock
Repetitive sequence of pulses
Useful for measuring duration of micro-ops
Must be long enough to allow signal propagation
Different control signals at different times within instruction cycle
Need a counter with different control signals for t1, t2 etc.

28. Control Unit with Decoded Inputs

29. Hardwired Control Unit Logic
For each control signal, to derive a Boolean expression of that signal as a function of the inputs
Let us consider a single control signal, C5, signal causes data to be read from the external data bus into the MBR
Let us define two new control signals, P and Q, that have the following interpretation:
PQ = 00 Fetch Cycle
PQ = 11 Interrupt Cycle
PQ = 10 Execute Cycle
PQ = 01 Indirect Cycle

30. Hardwired Control Unit Logic
Then C5 can be defined as:
C5 = P # Q # T2 + P # Q # T2
That is, the control signal C5 will be asserted during the second time unit of both the fetch and indirect cycles.
C5 is also needed during the execute cycle. For our simple example, let us assume that there are only three instructions that read from memory: LDA,ADD, and AND. Now we can define C5 as
C5 = P # Q # T2 + P # Q # T2 + P # Q # (LDA + ADD + AND) # T2

31. Hardwired Control Unit Logic
This same process could be repeated for every control signal generated by the processor. The result would be a set of Boolean equations that define the behavior of the control unit and hence of the processor.

32. Hardwired Control Unit Logic
To tie everything together, the control unit must control the state of the instruction cycle. As was mentioned, at the end of each subcycle (fetch, indirect, execute, interrupt), the control unit issues a signal that causes the timing generator to reinitialize and issue T1. The control unit must also set the appropriate values of P and Q to define the next subcycle to be performed

33. Problems With Hard Wired Designs
Complex sequencing & micro-operation logic
Difficult to design and test
Inflexible design
Difficult to add new instructions

34. Chapter 16 Micro-programmed Control

35. Control Unit Organization

36. Micro-programmed Control
Use sequences of instructions (see earlier notes) to control complex operations
Called micro-programming or firmware

37. Implementation (1)
All the control unit does is generate a set of control signals
Each control signal is on or off
Represent each control signal by a bit
Have a control word for each micro-operation
Have a sequence of control words for each machine code instruction
Add an address to specify the next micro-instruction, depending on conditions

38. Today’s large microprocessor
Implementation (2)
Today’s large microprocessor
Many instructions and associated register-level hardware
Many control points to be manipulated
This results in control memory that
Contains a large number of words
co-responding to the number of instructions to be executed
Has a wide word width
Due to the large number of control points to be manipulated

39. Micro-program Word Length
Based on 3 factors
Maximum number of simultaneous micro-operations supported
The way control information is represented or encoded
The way in which the next micro-instruction address is specified

40. Micro-instruction Types
Each micro-instruction specifies single (or few) micro-operations to be performed
(vertical micro-programming)
Each micro-instruction specifies many different micro-operations to be performed in parallel
(horizontal micro-programming)

41. Horizontal Micro-programming
Wide memory word
High degree of parallel operations possible
Little encoding of control information

42. Typical Microinstruction Formats

43. Organization of Control Memory

44. Control Unit

45. Control Unit Function Sequence login unit issues read command
Word specified in control address register is read into control buffer register
Control buffer register contents generates control signals and next address information
Sequence login loads new address into control buffer register based on next address information from control buffer register and ALU flags

46. Depending on ALU flags and control buffer register
Next Address Decision
Depending on ALU flags and control buffer register
Get next instruction
Add 1 to control address register
Jump to new routine based on jump microinstruction
Load address field of control buffer register into control address register
Jump to machine instruction routine
Load control address register based on opcode in IR

47. Functioning of Microprogrammed Control Unit