1. IR <2..0> CON 3-to-8 Decoder Never Branch Always Branch
BUS<31..0>
Never Branch 1
Always Branch
= 0
Branch if zero 32
CON
D Q
> 0
Bit <31> only Q
< 0
LCON
Branch if positive
Branch if not zero

2. Review

3. CS501 Advanced Computer Architecture
Lecture 16
Dr.Noor Muhammad Sheikh

4. Control signals for the br and brl instructions
Syntax: brzr rb, rc
Step
RTL for br
Control signals
T0-T2
Instruction Fetch
As before T3
CON cond(R[rc]);
LCON, RCE, R2BUS T4
CON: PC R[rb]
RBE, R2BUS, LPC (if CON=1)
For the branch and link instructions:
Syntax: brlzr ra, rb, rc
Step
RTL
Control signals
T0-T2
Instruction Fetch
As before T3
CON cond(R[rc]);
LCON, RCE, R2BUS T4
CON: R[ra] PC;
RAE, BUS2R, PCout (if CON=1) T5
CON: PC R[rb];
RBE, R2BUS, LPC (if CON=1)

5. Generating the test condition N=0… IR 4 31
count

6. Control signals for the shr instruction
Step
RTN for shr
Control signals
T0-T2
Instruction Fetch
As before T3
n<4..0> IR<4..0>; LN T4
(N = 0) : (n<4..0> R[rc]<4..0>);
LN(N=0), RCE, R2BUS T5
C (Nα0) © R[rb]<31..N>;
LC, SHR(N) T6
R[ra] C;
Cout, RAE, BUS2R

7. Hardwired Control Unit
Block diagram of a Hardwired Control Unit
signals from the data path
Hardwired Control Unit …
decoded op-code from the IR
output signals to various parts of the processor …
signals from external devices
timing step generator

8. … … Generating Control Signals
Based on the op-code in the Instruction Register for the FALCON-A
15 … 11
10…8 …
opcode ra
Instruction register
These are the control signal names
0 OP0 for add
5 to 32
decoder
1 OP1 for addi 1 2 3 4
2 OP2 for sub
3 OP3 for subi
4 OP4 for mul
5 OP5 for div …
These are the assembly language instruction mnemonics
Enable
31 OP31 for halt
Logic ‘1’
bit 11
bit 15

9. Boolean Equations for some control signals
S.No
Control
Signal
Boolean Equation 1
PCout
T0+T3.(OP20+OP22)+T4.(OP16+..+OP19) 2
LMAR
T0+T5.(OP28+OP29) 3
INC2 T0 4 LC
T3.(OP6+OP7+OP22..+OP25+OP14)+T4.(OP0+..OP3+OP8+..+OP13+OP15+OP20+OP28+OP29)+T5.(OP22+OP23+OP16+..OP19)+T6.(OP4+OP5) 5
Cout
T4.(OP6+OP7+OP24+OP25+OP22+OP23+OP14)+T5.(OP0+..OP5+OP8+..+OP13+OP15+OP20+OP28+OP29)+T6.(OP4+OP5+OP16+..+OP19) 6
LPC
T1+T5.OP20+T6.CON.(OP16+..OP19) 7
MBRout
T2+T7.(OP28+OP29) 8
LIR T2 9
BUS2R
T4.OP14+T5.(OP0+..+OP5+OP8+..OP11)+T7.OP29 10
R2BUS
T3.(OP0..+OP14) 11 LA
T3.(OP0+..+OP5+OP8+..+OP11+OP20+OP22+OP28+OP29)+T4.(OP16+..+OP19)

10. Logic generation for PCout PCout=T0+T3.(OP20+OP22)+T4.(OP16+..+OP19)

11. Logic generation for LPC
LPC=T1+T5.OP20+T6.CON.(OP16+..OP19)

12. Example: Calculating the maximum clock frequency for a circuit
Timing parameters:
Name
Parameter
FAST Delays
VITESSE
Delays
Gate propagation time tg
5 ns
150 ps
Bus propagation time tb
500 ps
Logic delay
tcomb
14 ns
~400ps
Flip-flop propagation time t1
6 ns
440 ps
Flip-flop setup time
tsu
2 ns
146 ps
Flip-flop hold time th
3 ns
104 ps
Flip-flop strobe width
twmin
4 ns NA

13. Example: Calculating the maximum clock frequency for a circuit
For the FAST TTL gates, the minimum clock period can be
calculated as,
tmin=tg+tbp+tcomb+tl
= =30ns+3ns(safety margin)=33ns
Hence the maximum clock frequency=1/(33x10-9)=30 MHz
Similarly, for VITESSE gate array the minimum clock
period is,
= =1490 ps+safety margin=1.6ns
Maximum clock frequency=1/(1.6x10-9)=625 MHz

14. A 2-bus implementation for the SRC
(“in bus”)
B bus
(“Out bus”) R0 32
General Purpose Registers 32 32
A 2-bus implementation for the SRC
R31
Both buses are “Internal processor buses” IR PC
MAR
MBR A A B
To External CPU Bus
ALSU C

15. Structural RTL for the sub instruction using the 2-bus data path implementation
Format: sub ra, rb, rc
Step
RTL T0
MAR PC; T1
MBR M[MAR], PC PC + 4; T2
IR MBR; T3
A R[rb]; T4
R[ra] A - R[rc];
Instruction Fetch
Instruction Execute
At the end of each sequence, the timing step generator is initialized to T0

16. Control Signals for the Fetch operation
Step
RTN
Control Signals T0
MAR PC;
PCout, LMAR, C=B; T1
MBR M[MAR], PC PC + 4;
PCout, INC4, LPC, MRead, MARout, LMBR; T2
IR MBR;
MBRout, C=B, LIR; T3
Instruction Execution