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MIPS Microarchitecture Multicycle Processor

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Presentation on theme: "MIPS Microarchitecture Multicycle Processor"— Presentation transcript:

1 MIPS Microarchitecture Multicycle Processor
Lecture 19 Digital Design and Computer Architecture Harris & Harris Morgan Kaufmann / Elsevier, 2007

2 Review: Single-Cycle Processor

3 Multicycle Processor Datapath
Building Blocks

4 Read Instruction

5 Read Source Operand (rs)

6 Read Source Operand (rs)

7 Sign-Extend the Immediate

8 Sign-Extend the Immediate

9 Add Base Address to the Offset

10 Load Data from Memory

11 Write Data Back to Register File

12 Increment PC by 4

13 Enhanced Datapath for sw

14 Enhanced Datapath for sw

15 Enhanced Datapath for R-Type

16 Enhanced Datapath for beq

17 Multicycle Processor Datapath

18 Multicycle Processor Datapath

19 Multicycle Processor Control

20 Multicycle Processor: R-Type

21 Multicycle Processor: lw

22 Multicycle Processor: beq

23 Control Unit?

24 Control Unit

25 Multicycle Processor: addi

26 Next Time Exceptions


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