1. UNIT-VIII 8051 Microcontroller Architecture Register set of 8051
Modes of timer operation
Serial port operation
Interrupt structure of 8051
Memory and I/O interfacing of 8051

2. Fig 8.1 Architecture of 8051

3. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
(RXD)P3.0
(TXD)P3.1
(T0)P3.4
(T1)P3.5
XTAL2
XTAL1
GND
(INT0)P3.2
(INT1)P3.3
(RD)P3.7
(WR)P3.6
Vcc
P0.0(AD0)
P0.1(AD1)
P0.2(AD2)
P0.3(AD3)
P0.4(AD4)
P0.5(AD5)
P0.6(AD6)
P0.7(AD7)
EA/VPP
ALE/PROG
PSEN
P2.7(A15)
P2.6(A14)
P2.5(A13)
P2.4(A12)
P2.3(A11)
P2.2(A10)
P2.1(A9)
P2.0(A8)
8051
Fig 8.2 Pin Description Of 8051

4. Register set of 8051
1.Accumulator (ACC or A) ACC act as an operand register, in case of some instructions. The ACC register, has been allotted an address in the on-chip special function register bank. 2. B-Register This register is used to store one of the operands for multiply and divide instructions. (In other instruction it is used as a scratch pad.) This register is considered as a special function register. 3. PSW-Program Status Word This set of flags contains the status information and is considered as one of the special function register. o

5. 4. SP-Stack Pointer
This 8-bit wide register is incremented before the data is stored onto the stack using push or call instructions. This register contains 8-bit stack top address.
Stack may be defined anywhere in the on-chip 128-byte RAM.
SP reg. initialized to 07. After each stack output it is incremented.
5. DTPR (Data Pointer)
This 16-bit register contain 16-bit external data RAM address.
DPH -- is higher byte
DPL – is lower byte

6. 6. Port 0 to 3 Latches & Drivers These are allotted to I/O ports
6. Port 0 to 3 Latches & Drivers These are allotted to I/O ports. These latches have been allotted addresses in the special function register bank using this addresses user can communicate with these ports i.e P0,P1,P2,P3. 7. Serial Data Buffer The serial data buffer internally contains two independent registers. One register is a transmit buffer which is a parallel-in serial-out register. Other register is a receiver buffer which is a serial-in parallel-out register. The serial data buffer is identified as SBUF and is one of the special function registers.
ers

7. 8. Timer Registers These two 16-bit registers can be accessed as their lower & upper bytes i.e Register 0 – TL0, TH0 Register 1 – TL1, TH1 All these register can be accessed using the 4 address allotted to them which lie in the SFR address range i.e 80h to FFh. 9. Control Registers The special function registers IP, IE, TMOD, TCON, SCON & PCON contain control and status information for interrupts, timers, counters and serial port. 10. Timing & Control unit This unit derives all the necessary timing and control signals required for the internal operation of the circuit. It also derives control signals required for controlling the external system bus.

8. 11. Instruction Register
This register decodes the opcode of an instruction to be executed and gives information to the timing and control unit to generate necessary signals for the execution of the instruction.
12. EPROM and Program Address Register (PAR)
These blocks provide an on-chip EPROM & a mechanism to internally address it (it is not in 8051).
13. RAM & RAM Address Registers
These blocks provide internal 128 bytes of RAM and a mechanism to internally address it.

9. 14. ALU TMP1 & TMP2 holds the operands, users cannot access. 15
14. ALU TMP1 & TMP2 holds the operands, users cannot access. 15. SFR Register Bank This is a set of SFRs(special function registers), which can be addressed using their respective address which lie in the range 80h to FFh.

10. Signals description of 8051
Vcc -- +5v power supply
Vss -- ground
Reset – It resets the It is an input pin and is active high
The high pulse must be high at least 2 machine cycles.
Upon applying a higwill h pulse to RST, the microcontroller will reset and all values in registers be lost.
ALE/PROG – ALE is valid only for external memory accesses. This pin acts as program pulse input during on-chip EPROM programming. ALE may be used for external timing and clocking purpose. One ALE pulse is skipped during each access to external data memory. The ALE pin is used for de-multiplexing the address and data by connecting to the G pin of the 74LS373 latch.

11. EA – External Access Enable pin
If it is low – indicates that the 8051 can address external program memory.
If it is high – indicates execution of programs in internal memory.
This pin also receives 21 volts for programming of the on-chip EPROM.
PSEN (Program Store Enable)
– it is an active low output signal that acts as a strobe to read the external program memory. This goes low during external program memory accesses.

12. Port 0 (P0.0 – P0.7)
– Port0 is an 8-bit bidirectional bit addressable I/O port. This has been allotted on address in the SFR address range. Port0 acts as multiplexed address/data lines during external memory access, i.e. when EA is and ALE emits a valid signal. In case of controllers with on-chip EPROM Port0 receives code bytes during programming of the internal EPROM.
Port 1 (P1.0 – P1.7)
– Port1 acts as an 8-bit bidirectional bit addressable. This has been allotted an address in the SFR address range.

13. Port 2 (P2.0 – P2.7)
– Port2 acts as an 8-bit bidirectional bit addressable. This has been allotted an address in the SFR address range. During external memory access, ports emits higher eight bits of address(A8-A15) which are valid, if ALE goes high and EA is low. P2 also receives higher order address bits during programming of the on-chip EPROM.
Port 3 (P3.0 – P3.7)
– Port3 acts as an 8-bit bidirectional bit addressable. This has been allotted an address in the SFR address range. The port3 pins also serve the alternative functions.

14. XTAL1 & XTAL2
-- There is an inbuilt oscillator which derives the necessary clock frequency for the operation of the controller.
XTAL1 – is the input of the amplifier
XTAL2 – is the output of the amplifier

15. Table 8.1 Alternate Functions of Pins of Port3
Port 3 pins
Alternative Function
P3.0
Acts as serial input data pin (RXD)
P3.1
Acts as serial output data pin (TXD)
P3.2
Acts as external interrupt pin 0 (INT0)
P3.3
Acts as external interrupt pin 1 (INT1)
P3.4
Acts as external input to timer 0 (T0)
P3.5
Acts as external input to timer 1 (T1)
P3.6
Acts as write control signal for external data memory write operation (WR)
P3.7
Acts as read control signal for external data memory read operation (RD)
Table 8.1 Alternate Functions of Pins of Port3

16. Addressing Modes
Immediate
Register
Direct
Register indirect
Indexed

17. Immediate Addressing Mode
MOV A,#25H ;load 25H into A
MOV R4,# ;load the decimal value 62 into R4
MOV B,#40H ;load 40H into B
MOV DPTR,#4521H ;DPTR=4521H
MOV DPTR,#2550H
;is the same as:
MOV DPL,#50H
MOV DPH,#25H

18. Register Addressing Mode
MOV A,R0 ;copy the contents of R0 into A
MOV R2,A ;copy the contents of A into R2
ADD A,R5 ;add the contents of R5 to contents of A
ADD A,R7 ;add the contents of R7 to contents of A
MOV R6,A ;save accumulator in R6
MOV DPTR,#25F5H
MOV R7,DPL
MOV R6,DPH

19. Direct Addressing Mode
MOV R0,40H ;save content of RAM location 40H in R0
MOV 56H,A ;save content of A in RAM location 56H
MOV R4,7FH ;move contents of RAM location 7FH to R4
MOV A,4 ;is same as
MOV A,R4 ;which means copy R4 into A
MOV A,7 ;is same as
MOV A,R7 ;which means copy R7 into A

20. Register Indirect Addressing Mode
MOV ;move contents of RAM location whose
;address is held by R0 into A
;move contents of B into RAM location
;whose address is held by R1

21. Index Addressing Mode DPTR: 16 bits
MOVC ; “C” means program (code) space ROM

22. Fig 8.3 TMOD Register

23. Fig 8.4 TCON register

25. Fig 8.5 Basics of serial communication

26. Fig 8.6 Types of serial communication

27. Fig 8.7 Asynchronous frame format

28. Fig 8.8 RS pin standard

29. Fig 8.9 RS pin standard

30. Fig 8.10 TTL to RS-232 Conversions

31. Fig 8.11 BAUD Rates(Bps)supported by IBM PC

32. SCON is an 8-bit register used to program the start bit, stop bit, and data
bits of data framing, among other things
Fig SCON Register

33. SBUF is an 8-bit register used solely for serial communication
For a byte data to be transferred via the TxD line, it must be placed in the SBUF
Register
The moment a byte is written into SBUF, it is framed with the start and stop bits and transferred serially via the TxD line
SBUF holds the byte of data when it is received by 8051 RxD line
When the bits are received serially via RxD, the 8051 deframes it by eliminating the stop and start bits, making a byte out of the data received, and then placing it in SBUF

34. Fig 8.13 PCON Register When 8051 is powered up, SMOD is zero
We can set it to high by software and thereby double the baud rate

35. Interrupts of 8051
An interrupt is an external or internal event that interrupts the microcontroller to inform it that a device needs its service
Polling can monitor the status of several devices and serve each of them as certain conditions are met

36. Interrupt sequence
1 . It finishes the instruction it is executing and saves the address of the next instruction (PC) on the stack
2. It also saves the current status of all the interrupts internally (i.e: not on the stack)
3. It jumps to a fixed location in memory, called the interrupt vector table, that holds the address of the ISR
4. The microcontroller gets the address of the ISR from the interrupt vector table and jumps to it
5. Upon executing the RETI instruction, the microcontroller returns to the place where it was interrupted

37. Types of 8051 interrupts Reset – power-up reset
Two interrupts are set aside for the timers:
one for timer 0 and one for timer 1
Two interrupts are set aside for hardware
external interrupts P3.2 and P3.3 are for the external hardware interrupts INT0 (or EX1), and INT1 (or EX2)
Serial communication has a single interrupt that belongs to both receive and transfer

38. Fig 8.14 Interrupt vector table

39. Fig 8.15 IE (interrupt enable) register

40. To enable an interrupt, we take the
following steps:
1. Bit D7 of the IE register (EA) must be set to high to allow the rest of register to take effect
2. The value of EA
If EA = 1, interrupts are enabled and will be responded to if their corresponding bits in IE are high
If EA = 0, no interrupt will be responded to, even if the associated bit in the IE register is high

41. Fig 8.16 Interrupts flag bits

42. Fig 8.17 Interrupt Priorities upon reset
We can alter the sequence of interrupt priority by assigning a higher priority to any one of the interrupts by programming a register called IP (interrupt priority)

43. Fig 8.18 Interrupt priority register

44. There are different types of read-only memory
PROM
EPROM
EEPROM
Flash EPROM
Mask ROM

45. The 8031 chip is a ROM less version of the 8051
It is exactly like any member of the 8051 family as far as executing the instructions and features are concerned, but it has no on-chip ROM
To make the 8031 execute 8051 code, it must be connected to external ROM memory containing the program code

46. Fig 8.19 Interfacing 8031 to external ROM

47. Fig 8.20 Interfacing 8031 with external data ROM and program ROM

48. Fig 8.21 Interfacing 8051 with external ROM

49. Fig interfacing with 8255

50. Fig connection to the 8255

51. Fig 8.24 8031 Connection to External Program ROM and the 8255

52. Fig 8.25 8255 Connection to Stepper Motor