1. SKIROC status
CERN – CALICE/EUDET electronic & DAQ meeting – 22/03/2007
Presented by Julien Fleury

2. Common DAQ Slice Timing is the same for all detectorsFE
FPGA
PHY
VFE
ASIC
Data
Clock+Config+Control
Conf/
Clock
Timing is the same for all detectors
Number of channels involves embedded electronic for all detectors
Outputting of data is done the same way for all detectors
 Back-end of very-front-end shall be common for all detectors
Detector
VFE Asic
FE electronic
Concentrator
FE of VFE
BE of VFE

3. Time considerations A/D conv. DAQ IDLE MODE 99% duty cycle
Time between two trains: 200ms (5 Hz)
time
Time between two bunch crossing: 337 ns
Train length bunch X (950 us)
analog detectors
only
Acquisition
A/D conv.
DAQ
IDLE MODE
1ms (.5%)
.5ms (.25%)
.5ms (.25%)
199ms (99%)
99% duty cycle
1% duty cycle

4. Read out : token ring Data bus Chip 0 A/D conv. DAQ IDLE MODE Chip 1
5 events
3 events
1 event
0 event
0 event
Chip 0
Chip 1
Chip 2
Chip 3
Chip 4
Data bus
Chip 0
A/D conv.
DAQ
IDLE MODE
Acquisition
Chip 1
A/D conv.
IDLE
DAQ
IDLE MODE
Acquisition
Chip 2
A/D conv.
IDLE
IDLE MODE
Acquisition
Chip 3
A/D conv.
IDLE
IDLE MODE
Acquisition
Chip 4
A/D conv.
IDLE
DAQ
IDLE MODE
Acquisition

5. Acquisition mode BCID N N+1 N+2 Trig OR Trigger_validb
No time measurement
 Synchronous hold validated by internal trigger
BCID N
N+1
N+2
Trig OR
Trigger_validb
Machine sync. Hold
Peaking time
Hold<k>
Valid_hold (analogue memory address) k k
k+1

6. SKIROC presentation ECAL read out Silicon PIN detector 36 channels
Compatible new DAQ

7. Main features Digital on FPGA for debug Designed for 5*5 mm² pads
36 channels (instead of 72 to reduce cost of prototype)
Detector AC/DC coupled
Auto-trigger
MIP/noise ratio on trigger channel : 16
2 gains / 12 bit ADC  2000 MIP
Energy resolution :4.89 (cf JCB)
MIP/noise ratio : 11
Power pulsing
Programmable stage by stage
Calibration injection capacitance
Embedded bandgap for references
Embedded DAC for trig threshold
Compatible with physic proto DAQ
Serial analogue output
External “force trigger”
Probe bus for debug
24 bits Bunch Crossing ID
SRAM with data formatting
Output & control with daisy-chain
Digital on FPGA for debug

8. 3-bit threshold adjustment
One channel
20M 1M
200ns
G=10
G=1
Analog Memory
Depth = 5
G=100
G=5
12 bits
ADC
Gain selection
0=>6pF
3-bit threshold adjustment
10-bit DAC
Common to the 36Channels T
100ns
DAC output Q
HOLD
Preamp
Ampli
Slow Shaper
Fast Shaper
Trigger
Charge measurement
3pF
Calibration input
input

9. Digital

10. Block scheme of SKIROC SRAM ECAL SLAB Analog mem. 36-channel Wilkinson
Analog channel
Analog mem.
36-channel
Wilkinson
ADC
Event
builder
Main
Memory
SRAM
Ch. 0
Analog channel
Analog mem.
Ch. 1
ECAL SLAB
Analog channel
Analog mem.
Ch. 35
24 bit counter
Time
digital mem.
Bunch crossing
Com
module
Trigger
control
Memory
pointer

11. SKIROC : RAM Mapping 15 7 ..................... 5 Time stamp (BCID)
Chip ID (8 bits)
Time stamp (12 bits)
Time stamp (12 bits) 5
Time stamp (BCID)
Time stamp (12 bits)
ADC measurement (12 bits)
0 0
ADC measurement (12 bits)
0 0
5x36
Hit (1 bit)
Gain (1 bit)
Charge Measurement
ADC measurement (12 bits)
185
0 0

12. STATUS Chips are due this month Testboard is in fab
MPW delayed by a couple of weeks
Testboard is in fab
5 PCBs are due for next week
Assembling in house
Firmware is in developpment
Labview software is in development
First results for the next CALICE meeting
Some more at LCWS