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Out-of-Order Execution Structures Optimizations

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Presentation on theme: "Out-of-Order Execution Structures Optimizations"— Presentation transcript:

1 Out-of-Order Execution Structures Optimizations
A. Moshovos © ECE Fall ‘07 ECE Toronto

2 Tag Elimination A. Moshovos © ECE Fall ‘07 ECE Toronto

3 Conventional Schedulers are Overdesigned
For MIPS-like ISA Two source tags One destination tag Not all instructions use two source operands Eg, addi $1, $2, 10 Not all instructions produce a result that is interesting for scheduling E.g., beq Some operands are ready when the instruction enters the scheduler Source: Efficient Dynamic Scheduling Through Tag Elimination, Dan Ernst and Todd Austin, ISCA 2002 A. Moshovos © ECE Fall ‘07 ECE Toronto

4 Some Operands are Ready when the Instruction Enters the Scheduler
A. Moshovos © ECE Fall ‘07 ECE Toronto

5 Window Specialization
Have reservation stations with different source operand wait capabilities A. Moshovos © ECE Fall ‘07 ECE Toronto

6 Window Specialization
At rename check how many source operands are not ready If there is an appropriate slot proceed to schedule If not, stall at rename Advantages: Destination bus only runs over reservation stations with comparators Load on the destination bus is reduced Disadvantages: Stalls due to unavailability of reservation stations Complexity of res. Station assignment A. Moshovos © ECE Fall ‘07 ECE Toronto

7 Window Specialization - Performance
Performance as IPC – Actual Clock Frequency not considered A. Moshovos © ECE Fall ‘07 ECE Toronto

8 Window Specialization - Performance
Performance as IPC per ns A. Moshovos © ECE Fall ‘07 ECE Toronto

9 Last Tag Prediction Observe:
Instruction becomes ready after the last tag it waits for appears Last Tag prediction Predict which of the two tags will that be Speculatively execute Correct speculation: that was the last tag Incorrect speculation: Need to reschedule Detection? Try to read a value that is not available A. Moshovos © ECE Fall ‘07 ECE Toronto

10 GShare-Style Last Tag Prediction
Two-bit saturating counters A. Moshovos © ECE Fall ‘07 ECE Toronto

11 Accuracy Over all instructions with two outstanding operands
A. Moshovos © ECE Fall ‘07 ECE Toronto

12 Window Specialization - Performance
Performance as IPC – Actual Clock Frequency not considered A. Moshovos © ECE Fall ‘07 ECE Toronto

13 Window Specialization - Performance
Performance as IPC per ns A. Moshovos © ECE Fall ‘07 ECE Toronto

14 Prescheduling Data-flow prescheduling for large
instruction windows in out-of-order processors Pierre Michaud, André Seznec, HPCA 2001 A. Moshovos © ECE Fall ‘07 ECE Toronto

15 Prescheduling Predict latencies Put scheduled instructions into a FIFO
Slide into a smaller window A. Moshovos © ECE Fall ‘07 ECE Toronto

16 Prescheduling Method A. Moshovos © ECE Fall ‘07 ECE Toronto

17 Prescheduling Example
A. Moshovos © ECE Fall ‘07 ECE Toronto

18 Latency Prediction A. Moshovos © ECE Fall ‘07 ECE Toronto

19 Latency Prediction Contd.
A. Moshovos © ECE Fall ‘07 ECE Toronto

20 Broadcast Free Scheduler
A. Moshovos © ECE Fall ‘07 ECE Toronto

21 Broadcast Free Scheduler
Cyclone design D. Ernst, A. Hamel, T. Austin ISCA 2003 Preschedule Instructions Put them into a dual strip cyclical FIFO Vertical paths allow for motion between the strips A. Moshovos © ECE Fall ‘07 ECE Toronto

22 Cyclone Architecture Will be ready in cycle + 6 A. Moshovos ©
ECE Fall ‘07 ECE Toronto

23 Cyclone Architecture – Cycle +1
A. Moshovos © ECE Fall ‘07 ECE Toronto

24 Cyclone Architecture – Cycle + 2
A. Moshovos © ECE Fall ‘07 ECE Toronto

25 Cyclone Architecture – Cycle + 3
A. Moshovos © ECE Fall ‘07 ECE Toronto

26 Cyclone Architecture – Cycle + 4
A. Moshovos © ECE Fall ‘07 ECE Toronto

27 Cyclone Architecture – Cycle + 5
A. Moshovos © ECE Fall ‘07 ECE Toronto

28 Cyclone Architecture – Cycle + 6
A. Moshovos © ECE Fall ‘07 ECE Toronto

29 Cyclone Architecture – Cycle + 6
A. Moshovos © ECE Fall ‘07 ECE Toronto

30 Cyclone Architecture – Mis-scheduling
Estimate new latency A. Moshovos © ECE Fall ‘07 ECE Toronto

31 Pre-scheduler Can only do two cascaded MAX calculations
Due to timing considerations Insert instruction with predicted latency N at the front of the FIFO Have it switch at N/2 A. Moshovos © ECE Fall ‘07 ECE Toronto

32 Cyclone IPC Performance
A. Moshovos © ECE Fall ‘07 ECE Toronto

33 Cyclone True Performance and Area
A. Moshovos © ECE Fall ‘07 ECE Toronto

34 Matrix Schedulers A. Moshovos © ECE Fall ‘07 ECE Toronto

35 Conventional Scheduler
IW grants WS requests A. Moshovos © ECE Fall ‘07 ECE Toronto

36 Conventional Scheduler Timing
B1 B3 B1 Can’t pipeline without introducing Bubbles between dependent Instructions: A2 Source: A High-Speed Dynamic Instruction Scheduling Scheme for Superscalar Processors Masahiro Goshima Kengo Nishino Yasuhiko Nakashima Shin-ichiro Mori Toshiaki Kitamura Shinji Tomita MICRO 2001 B3 A. Moshovos © ECE Fall ‘07 ECE Toronto

37 Towards a Matrix Scheduler
Observe: In conventional scheduling dependences are discovered twice: Once at renaming Once during scheduling Why? Dependences are implicitly represented Producer and Consumer link via a name This is indirect Matrix Scheduler idea: Represent dependences explicitly A. Moshovos © ECE Fall ‘07 ECE Toronto

38 Dependence Matrix Who do I depend upon? Left source Right source
Who am I A. Moshovos © ECE Fall ‘07 ECE Toronto

39 Matrix Scheduler Write port wakeup A. Moshovos ©
ECE Fall ‘07 ECE Toronto

40 Inserting an entry Write port A. Moshovos ©
ECE Fall ‘07 ECE Toronto

41 Wakeup wakeup A. Moshovos © ECE Fall ‘07 ECE Toronto

42 Mispeculation Recovery
Do not cleanup Use external logic to inhibit request signals A. Moshovos © ECE Fall ‘07 ECE Toronto

43 Delay 0.18um 1.8V Partial wakeup lines 1.Matrix 85C 2. RAM+CAM
Match to ready Delay Issue to cells 0.18um 1.8V 85C Partial wakeup lines 1.Matrix 2. RAM+CAM A. Moshovos © ECE Fall ‘07 ECE Toronto

44 Delay measurement points
A. Moshovos © ECE Fall ‘07 ECE Toronto

45 Scheduling Priorities
A. Moshovos © ECE Fall ‘07 ECE Toronto

46 Conflict Resolution More instructions ready than available issue slots
Which get to go? Age vs. Pseudo-Random Resolution Age is important Priority Enforcer picks the oldest Complex Source: Matrix Scheduler Reloaded ISCA 2007 A. Moshovos © ECE Fall ‘07 ECE Toronto

47 Compacting Scheduler Implemented in the Alpha 21264
Physical order within scheduler corresponds to age Entry freed: Shift up all younger entries A. Moshovos © ECE Fall ‘07 ECE Toronto

48 Goal A. Moshovos © ECE Fall ‘07 ECE Toronto

49 Virtual Physical Registers
Physical register names are used for two purposes Scheduling Communicating A physical register is held much in advance than needed We need the register only after the value is produced De-couple scheduling from communication names A. Moshovos © ECE Fall ‘07 ECE Toronto

50 Used vs. Allocated Registers
A. Moshovos © ECE Fall ‘07 ECE Toronto

51 Virtual Physical Registers
A. Moshovos © ECE Fall ‘07 ECE Toronto

52 Deadlock Older instruction completes later than younger ones
No registers available Steal a register and re-execute A. Moshovos © ECE Fall ‘07 ECE Toronto

53 Performance vs. Physical Registers
A. Moshovos © ECE Fall ‘07 ECE Toronto

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