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CS/COE0447 Computer Organization & Assembly Language

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Presentation on theme: "CS/COE0447 Computer Organization & Assembly Language"— Presentation transcript:

1 CS/COE0447 Computer Organization & Assembly Language
Logic Design

2 Logic Design Digital hardware is implemented by way of “logic design”
Digital circuits process and produce two discrete values: 0 and 1 Example: 1-bit full adder (FA)

3 Layered Design Logic design is done using logic gates
Often we design desired function using high-level languages at somewhat higher level than logic gates Microarchitecture Function blocks Logic gates Transistors

4 Logic Gates 2-input AND Y=A&B Y=A|B 2-input OR 2-input NAND Y=~(A&B)
2-input NOR Y=~(A|B) Y B

5 Function Impl. Using Gates
? inputs outputs

6 Describing a Function OutputA = F(Input0, Input1, …, InputN-1)
OutputB = F’(Input0, Input1, …, InputN-1) OutputC = F’’(Input0, Input1, …, InputN-1) Methods Truth table Sum of products Product of sums

7 Truth Table Input Output A B Cin S Cout 1

8 Truth Table, Cont’d S = A’B’Cin+A’BCin’+AB’Cin’+ABCin
Input Output A B Cin S Cout 1 S = A’B’Cin+A’BCin’+AB’Cin’+ABCin Cout = A’BCin+AB’Cin+ABCin’+ABCin

9 Combinational vs. Sequential Logic
Combinational logic A function whose outputs are dependent only on the current input As soon as inputs are known, outputs can be computed Sequential logic Some memory elements (i.e., state) Outputs are dependent on current state and current input Next state is dependent on current state and current input

10 Combinational Logic inputs outputs

11 Sequential Logic inputs outputs next state current state clock

12 Implementing Combinational Logic
Any combinational logic can be implemented using sum of products or product of sums Input-output relationship can be defined in a truth table From a truth table, each output function can be derived Boolean expressions can be further manipulated using various Boolean algebraic principles

13 Boolean Algebra Boole, George (1815~1864): mathematician and philosopher; inventor of Boolean Algebra, the basis of all computer arithmetic Binary values: 0, 1 Two binary operations: AND (/), OR () One unary operation: NOT (~)

14 Boolean Algebra, cont’d
Binary operations: AND (/), OR () Idempotent aa = a+a = a Commutative ab = ba a+b = b+a Associative a(bc) = (ab)c a+(b+c) = (a+b)+c Distributive a(b+c) = ab + ac a+(bc) = (a+b)(a+c)

15 Boolean Algebra, cont’d
De Morgan’s laws ~(a+b) = ~a~b ~(ab) = ~a+~b More… a+(ab) = a a(a+b) = a ~~a=a a+~a = 1 a(~a) = 0

16 Expressive Power With AND/OR/NOT, we can express any function in Boolean algebra Indeed, any combination logic can be implemented using AND/OR/NOT gate Sum of products Nand and Nor gates are Universal: all boolean functions can be implemented using only Nand gates, or only Nor gates In Lecture: we showed this for Nand gates

17 Multiplexor In lecture, we saw a gate implementation of a MUX A Y B 1
Y B 1 S Y = (S) ? B:A;

18 A 32-bit Multiplexor

19 Simplifying Expressions
Think of Cout in our Adder Cout = A’BCin+AB’Cin+ABCin’+ABCin Cout = BCin+ACin+AB Input Output A B Cin S Cout 1

20 Karnaugh Map [not covered Sp 2007]
1 BCin 00 ACin 01 1 11 1 1 BCin 10 1 AB Cout = BCin+AB+ACin

21 Implementing Comb. Logic
PLA (Programming Logic Array) A direct implementation of sum of products form pla.html (thanks to: ROM (Read Only Memory) Interpret the truth table as fixed values stored in memory Using logic gate chips (74LS…)

22 74LS Series Chips contain several logic gates 2-input OR gate
SN 74LS04 Hex inverter gate SN 74LS08 Quad 2-input AND gate SN 74LS32 Quad 2-input OR gate

23 Building a 1-bit ALU ALU = Arithmetic Logic Unit

24 Building a 32-bit ALU

25 Implementing “SUB”

26 Implementing “NAND”/”NOR”

27 Implementing “SLT”

28 Implementing “SLT”, cont’d

29 Supporting “BEQ”/”BNE”
Need a “zero-detector”

30 ALU Symbol Note that it’s a combinational logic

31 ALU Control (figure 5.12)

32 ALU Control Logic Design For single-cycle control (multi-cycle involves the clock)

33 End of the material covered
Spring 2007

34 RS Latch Note that there are feedbacks!

35 RS Latch, cont’d 1 1 1 When R=0, S=1

36 RS Latch, cont’d 1 1 1 When R=1, S=0

37 RS Latch, cont’d 1 1 When R=0, S=0, and Q was 0

38 RS Latch, cont’d 1 1 When R=0, S=0, and Q was 1

39 RS Latch, cont’d 1 1 What happens if R=S=1?

40 D Latch Note that we have an R-S latch as a back-end

41 D Latch, cont’d R S Note that S, R inputs always get inverted input of D when C=1 When C=0, S=R=0, remembering the previous value

42 D Latch, cont’d R C D Q(t) Q(t-1) 1 S

43 D Latch, cont’d D Q D Latch C Q’

44 D Flip-Flop (D-FF) Two D latches are cascaded, with opposite clock

45 D Flip-Flop, cont’d D Q D-FF C Q’

46 Register File Implementation we’ll return to this in appendix B

47 Reg. File Impl., cont’d we’ll return to this in appendix B
1 1 1 1 1 0x 0x

48 To Summarize… In digital logic, transistors are used as simple switches Logic gate is an abstraction of multiple transistor network A combinational logic block has inputs and outputs that depend on the current inputs A sequential logic block is composed of some combinational logic and memory that keeps the current state

49 To Summarize…, cont’d Boolean algebra provides theory for digital logic Combinational logic can be implemented using PLA (and many other methods) An ALU for MIPS architecture has been built!

50 To Summarize…, cont’d Flip-flops were used as a memory element
An FSM can be implemented using FFs and some combinational logic


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