1. Reliability simulation implementation in Cadence - HiCuM/L2 example
Thomas Zimmer *
Oskar Holstensson**
Bertrand Ardouin**
* Université de Bordeaux
** XMOD Technologies
Reliability simulation implementation in Cadence - HiCuM/L2 example

2. OUTLINE Context Introduction Proposed transistor aging model
Why a dynamic ageing model?
Proposed transistor aging model
VerilogA implementation in HiCuM model
Practical implementation in Cadence Virtuoso
Conclusion

3. We are talking here about “dynamic ageing model”
CONTEXT
We are talking here about “dynamic ageing model”

4. WHY A DYNAMIC AGEING MODEL ?
Need to integrate stress conditions:
degradation = f(Time, Voltage, Temperature, Device geometry)
Ageing is a dynamic phenomenon !
It does not depend only on “quiescent” bias point but on the integration of voltage impact over time
Degradation occurs dynamically
Limit for hot carrier degradation
DC operating point is below, predicts no degradation

5. Why dynamic aging ?
Some static models (e.g., Scholten et al, [6]) integrate stress conditions over one or a few circuit periods and then extrapolate degradation / lifetime
so why do we still need a dynamic model at all ?
Stress conditions can evolve over circuit life cycle
negative or positive feedback effect
i.e. saturation of degradation, or exponential growth of degradation.

6. Why dynamic aging ? Dynamic aging model in red
Static aging model in green
(constant degradation rate)
Degradation (of a FoM) depends on stress time and degradation rate
Degradation rate ultimately depends on stress conditions
BUT :
Stress conditions can be a function of (long term) stress time
Stress conditions depend on environment (Circuit architecture)
FoM
Lifetime FoM limit t0
Stress time t0
Stress time
Stress starts at t0

7. Why dynamic aging ?
Example circuit above
Q4 is stressed, its VBE drifts during circuit life cycle:
Ibias changes
IC of Q1 and Q2 change
VCE of Q1 and Q2 change (Electric field responsible for HCI voltage change)
After a few years, the degradation rate is different compared to t=0.
Ibias
Degradation rate of Q1/Q2 t0
Stress time
Dynamic Aging allows observing degradation effects “LIVE”

8. EXAMPLE: InP HBT process
Stress the device for ~1000 different stress conditions (P1, P2, … P4)
Monitor Gummel characteristic:
Plot IC and  IB vs stress time
For this specific experimental case, the degradation rate is constant vs stress time
∆P(t)=K(Bias,temp)
But more complex degradation laws can be (and have also been) used instead such as:
∆P(t)= Pmax 1+ 𝑡 𝐾( 𝑏𝑖𝑎𝑠,𝑡𝑒𝑚𝑝 ) −𝛼

9. PROPOSED TRANSISTOR AGING MODEL
Some model parameters become now function of time
Collector current equation:
Base current equation
IS and IBEIS follow the same linear evolution as traps with stress time
IS and IBEIS can be advantageously used as variables of the aging model

10. PROPOSED TRANSISTOR AGING MODEL
Degradation rates are constant vs time and depend on temperature and bias
IBEIS and IS are modeled according a generation mechanism The constant increasing rates follow an Arrhenius law new model parameters : EIS, EIBEIS, BIBEIS, BIS
[5] C. Mukherjee, B. Ardouin, J-Y Dupuy, V. Nodjiadjim, M.l Riet, T. Zimmer, F. Marc, and Cristell Maneux, “Reliability-Aware Circuit Design Methodology for Beyond-5G Communication Systems”, IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 17, NO. 3, SEPTEMBER 2017

11. VERILOGA IMPLEMENTATION IN HiCuM
The new equations are implemented as extra model nodes in HiCuM/L2
Ibeis_out
AIBEIS
C=1
Is_out
AIS
C=1
2 new nodes
The output voltage at the new nodes provide
directly P(t) dynamically

12. How to use aging models ?
STEP 1
STEP 1: Run the initial “stress” simulation to calculate the amount of degradation for each transistor in a circuit
Observe degradations “LIVE” -> take countermeasures (transistor sizing, circuit architecture modification, gain compensation loops, etc.)
Map transistor degradations in the circuit -> “extract” skewed model parameters @ Age time for subsequent step 2 10
(years)

13. How to use aging models ?
STEP 2
STEP 2 Run simulations with post-stress model cards (one per transistor instance)
Circuit Pass / Fail reliability criteria
DC, transient, AC, S parameters, harmonic balance, … simulations of stressed circuits
Plot FoMs versus circuit life time
System architecture validation

14. EDA FLOW INTEGRATION XMOD’s VintageDFR Plugin in Cadence Virtuoso
Vintage: VerilogA Integration of a Aging
DFR: Design For Reliability

15. EDA FLOW INTEGRATION STEP 1 Open aging settings Run stress simulation
Age of circuit

16. EDA FLOW INTEGRATION
STEP 2
Run post stress simulation

17. SPECTRE Integration
Custom netlisting procedure substitutes aging models to standard foundry models
Implemented in SKILL, Virtuoso’s scripting language
Aging models used only during stress simulations (step 1)
Standard models used for post-stress simulations
STEP 1
STEP 2

18. Aging : Standard Netlist
Default SPECTRE
Netlister
model PMOSMOD bsim4 VTH= -0.5 U0= 100 …
model NMOSMOD bsim U0= 140 …
model HBTHS hicum c10 =1e-34 …
include "PDK_standard.scs"
M1 (OUT A VDD) PMOSMOD W=2u L=0.13n
M2 (OUT B GND) NMOSMOD W=1u L=0.13n
...

19. Aging : Patched Netlist
Selectively substitute device models for aging
STEP 1
model PMOSMOD bsim4 VTH= -0.5 U0= 100 …
model NMOSMOD bsim U0= 140 …
model HBTHS hicum c10 =1e-34 …
Patched SPECTRE
Netlister
include "PDK_standard.scs"
M1 (OUT A VDD) PMOSMOD W=2u L=0.13n
M2 (OUT B GND) NMOSMOD W=1u L=0.13n
...
model PMOSMOD_AGING bsim4_ag VTH= -0.5 …
model NMOSMOD_AGING bsim4_ag VTH= 0.5 …
model HBT_AGING hicum_ag c10 =1e-34 …
include "PDK_aging.scs"
M1 (OUT A VDD) PMOSMOD_AGING W=2u L=0.13n
M2 (OUT B GND) NMOSMOD_AGING W=1u L=0.13n

20. Aging : Stress Simulation
include "PDK_aging.scs"
M1 (OUT A VDD) PMOSMOD_AGING W=2u L=0.13n
M2 (OUT B GND) NMOSMOD_AGING W=1u L=0.13n
STEP 1
SPECTRE
Simulator
Simulate aging with applied stress
Aging simulation results

21. Aging : Results Extraction
STEP 1
Aging simulation results
SKILL Result Extractor
Extract and store aging data
Age file
End of step 1

22. Aging : “Alter” Netlist
Start of step 2
STEP 2
Age file
Custom C Code
Age of circuit
Alt0 ALTER SUB=M1 PARAM=U0 VALUE=...
Alt1 ALTER SUB=M1 PARAM=VTH VALUE=...
Alt2 ALTER SUB=M2 PARAM=U0 VALUE=...
...
Create a netlist altering the parameters of the aged devices

23. Aging : Aged Simulation
Alt0 ALTER SUB=M1 PARAM=U0 VALUE=...
Alt1 ALTER SUB=M1 PARAM=VTH VALUE=...
Alt2 ALTER SUB=M2 PARAM=U0 VALUE=...
...
STEP 2
Default SPECTRE
Netlister
SPECTRE
Simulator
include "PDK_standard.scs"
M1 (OUT A VDD) PMOSMOD W=2u L=0.13n
M2 (OUT B GND) NMOSMOD W=1u L=0.13n
...
Aged circuit simulation results
Simulate with the original netlist to obtain aged simulation results
End of step 2

24. Settings : Stress Conditions
Stress duration
ATSF= Stress duration Simulation time
Choose stress conditions
Simulation time

25. Settings : Device Models
Select models to age

26. Settings : Calculator Wizard
Use wizard to find appropriate simulation acceleration factors

27. CONCLUSION Specific Tool developed by XMOD :
VintageDFR Plugin in Cadence Virtuoso
Supports customer VerilogA model (researchers can focus on theoretical modeling, professional EDA integration is straightforward )
Support Diodes, Bipolar, MOS and HV-MOS
Support Hot Carrier, NBTI (and recovery)
verilogA allows virtually any dynamic aging equations
Support Self-heating
Tightly integrated with Cadence flow

28. REFERENCES
[1] Geoffrey J. Coram, “HOWTO (AND HOW NOT TO) WRITE A COMPACT MODEL IN VERILOG-A”, Proc. BMAS 2004)
[2] F. Marc, B. Mongellaz, C. Bestory, H. Levi, Y. Danto. “Improvement of aging simulation of electronic circuits using behavioral modeling”. IEEE Transactions on Device and Materials Reliability, 6 :228–234, 2006
[3] M. Schröter, “High-frequency circuit design oriented compact bipolar transistor modeling with HICUM”, IEICE Transactions on Electronics, Special Issue on Analog Circuit and Device Technologies, Vol. E88-C, No. 6, pp , 2005
[4] B. Ardouin, J.-Y. Dupuy , J. Godin, V. Nodjiadjim, M. Riet, F. Marc, G. A. Koné, S. Ghosh, B. Grandchamp, C. Maneux, “Advancements on Reliability-Aware Analog Circuit Design” (Invited), Proceedings of the ESSDERC Conference, Sep. 2012, pp
[5] C. Mukherjee, B. Ardouin, J-Y Dupuy, V. Nodjiadjim, M.l Riet, T. Zimmer, F. Marc, and Cristell Maneux, “Reliability-Aware Circuit Design Methodology for Beyond-5G Communication Systems”, IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 17, NO. 3, SEPTEMBER 2017
[6] Andries J. Scholten, Daniel Stephens, Geert D.J. Smit, Guido T. Sasse, Member, IEEE, and
Jaap Bisschop, “The Relation Between Degradation Under DC and RF Stress Conditions”, 2011, IEEE TED