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241-440 Computer System Design Lecture 9
Wannarat Suntiamorntut W.S.
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Memory Technology W.S.
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Technology Trend Capacity Speed Logic : 2x in 3 years 2x in 3 years
DRAM : 4x in 3 years 2x in 10 years Disk : 4x in 3 years 2x in 10 years W.S.
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Processor-DRAM memory Gap
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Expanded of Memory System
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Hierarchy of Modern computer
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How hierarchy manage? Registers <--> Memory by compiler
Cache <--> Memory by Hardware Memory <--> Disks by Hardware/OS, programmer (files) W.S.
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Logic Diagram of a Typical SRAM
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Typical of SRAM Timing W.S.
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Classical DRAM Organization
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Logic Diagram of a Typical DRAM
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Art of Memory Design W.S.
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1 KB Direct Mapped Cache with 32 B Blocks
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Example : Fully Associative
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A Two-way Set Associative Cache
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Disadvantage of Set Associative Cache
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How do you Design Cache? W.S.
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1 KB Direct mapped Cache, 32B blocks
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Improvement of Cache Reduce Miss rate Reduce Miss penalty
Reduce time to hit in cache W.S.
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Where can a block be placed in the upper level?
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Example W.S.
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Next on Lecture 10 W.S.
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