1. Complementary input stage with rail-to-rail Vicmr and constant gm
aIp Ip
aIn
3(Ip-In)
aIn
a(Ip-In) BP
Vbp
in+
in-
NC1,2
PC1,2 N1 P1 P2 N2
Vi+
Vi-
Vi+
Vi-
Vi-
Vi+
ip+
ip- BN
Vbn
3(In-Ip)
aIp
aIn In
aIp
a:3 1 2 3 4
a(In-Ip)

2. Folded cascode stage: summing current and convert to voltage
Vxx
in+ =+gmn1*vid/2
in- = -gmn1*vid/2
ip+ =+gmp1*vid/2
ip- = -gmp1*vid/2
io1- =ip- - in+ = -(gmp1+gmn1)*vid/2
io1+=ip+ - in- = (gmp1+gmn1)*vid/2
Vo1- = io1- /go1
Vo1+ = io1+ /go1
Vo1d = (Vo1+ -Vo1+ )
= vid *(gmp1+gmn1)/go1
in+
in-
Vyy
-in+
Vo1+
Vo1-
io1-=ip- - in+
Vbb
-ip-
ip+
ip-
Vzz

3. Dual n-channel input io1- = i- = -(gm1+gms1)*vid/2
Vo1- = io1- /go1
Vo1+ = io1+ /go1
Vo1d = (Vo1+ -Vo1+ ) = vid *(gm1+gms1)/go1 i+
ins+
ins- i-
in+
in-

4. Second stage M4
Vxx M4 M7 M7
Vyy M3 M3
Vbb M2 M2 M6 M6 M1
Vzz M1

5. Second stage push pull: Monticelli style
Vxx M4 M7 M7
Vyy M3 M3
Vbp
Vbn
Vbb M2 M2 M6 M6 M1
Vzz M1
Requires: VDD-VSS > Vgs6+Vgs7+Vdssat_floating_CS + Vo1 swing
Vo1 swing could b2 +- 2~3 time Veff6,7

6. Unpredictable current in second stage
Don’t do M4
Vxx M4 M7 M7
Vyy M3 M3
Vbb M2 M2 M6 M6 M1
Vzz M1
Unpredictable current in second stage

7. Low Voltage Push-pull output
Main goal: make Vo swing from Vss to Vdd.
Equivalent to double the output stage gm, ↑gain, GB
Make slew rate higher than Io/CL
1:M
Io/M Io
1:M
Make output Vebo small. When Vo1 swings, say by 2.1Vebo, ICL can be 10xIo!
But quiescent Io depends on Vo1Q, and uncontrolled.

8. In order for M6 and M7 to have well defined quiescent current, we have to bias the circuit so that at Q, Vd2 = Vg6Q to establish correct quiescent current in M6. This must be through current mirror ratio.
Problem:
Vd2 is a high impedance node, small current mismatch in M1 and M4 leads to significant voltage change at vd2, which in turn changes the biasing current in the output stage.
Solution:
use feedback to stabilize common mode of Vd2.
Vzz

9. Vzz
Vd2L
Vd2R
Feedback to
M4 or part of it
Since Vd2L and Vd2R are normally nearly constant. We do not need to worry about the input range accommodation for this circuit.
Size the circuit so that, when vid =0, Id6 remain near desired level over all process variations in M1 and M4.

10. Output quiescent current control by local CMFB.
Vo1 CMFB
1:M
Itail
Io/M
Io/M Io
1:M
1:1
match

11. Output quiescent current control by local CMFB.
Vo1 CMFB
1:M
Itail
Io/M
Io/M Io
1:M
1:1
match

12. Can passive CM detector be use?

13. M1a+M1b forms diff pair with M2
Vo1+/- swing is about +- 2.# * Vebo, or about to 0.4 V, so M1a and M1b should have Veb about equal to 2*Vebo.
Vb3 should be selected so that M12 is still in saturation when Vo1 drops to a little below Vthn-Vebo.
The Veb of M12, M10, and the size of diode connected CMFB1 transistor should be such that M 10 is guaranteed to be in saturation.
Note that there is only one high impedance node (Vo1 node) in this CMFB loop, hence the loop UGF can be made high and still maintain good stability.

14. Vo+ and Vo- also need common mode stabilization
M17t and M21t are in triode
M21t
M17t
M21
M17
M18
Vocmd
M19
M15 R R C C
M20
M16
Choose R to a couple times bigger than Ro
Choose C to be near or a couple times larger than Cgs of CMFB circuit.

15. M:1
1:M
Vxx
Vxx
M:1
1:M
Vocmd R R C C

16. Why RC in common mode detector
KCL at V:
(V1 – V)/R + (V2 – V)/R = V * sCgs
(V1 + V2)/R = V(sCgs + 2/R)
V = (V1 + V2)/2 * 1/(1 + sRCgs/2)
When |s| =|jw| << 2/RCgs,
V ≈ (V1 + V2)/2
Otherwise V is not close to common mode
To have CM detector work up to GB,
R << 2/(2pGB*Cgs) V1 R V
Cgs R V2

17. Why RC in common mode detector
KCL at V:
(V1 – V)(1/R +sC) + (V2 – V) (1/R +sC)
= V * sCgs
(V1 + V2) (1/R +sC) = V(sCgs + 2/R +2sC)
V = (V1 + V2)/2 *
(1 + sRC)/(1 + sRC + sRCgs/2)
As long as Cgs/2 < C, at all freq:
V ≈ (V1 + V2)/2 V1 R C V
Cgs C R V2
Hence, the RC network acts as a better CM detector

18. Why CMBF to M17t instead of first stage:
For CM behavior, assume DM=0.
Vo1+=Vo1-, and Vo+=Vo-=Vocm.
Without CMFB effect, at Q, Vo+ will be equal to Vg, which may be far below desired Vocm level.
With CMFB connected, the feedback effect will drive Vo1 so as to move Vo+ up to the desired Vocm level.
Since Vo1+ and Vo1- have a competing action on Vo+, it may take quite bit Vo1 movement to achieve the desired Vo+ movement, causing the biasing current in the second stage to be much larger than what is intended.
Vo1+
Vo1-
Vo+ Vg

19. Compensation for diff signal path’s closed-loop stability
Vxx M4 M7 M7
Vyy M3 M3 CC CC
Vbb M2 M2 M6 M6 M1
Vzz M1
Standard lead compensation

20. Alternative compensation: Ahuja
Vxx M4 M7 M7
Vyy M3 M3 CC CC
Vbb M2 M2 M6 M6 M1
Vzz M1
Also called indirect compensation.

21. Indirect Feedback - History
First proposed by B.K. Ahuja in “AN IMPROVED FREQUENCY COMPENSATION TECHNIQUE FOR CMOS OPERATIONAL-AMPLIFIERS,” Ieee Journal of Solid-State Circuits, vol. 18, no. 6, pp , 1983
However it is still seldom used in practice ??
Looks very similar to Miller compensation
Prompts most designers to use design strategy for Miller-Rz compensation
However the Indirect Compensation Scheme has different pole/zero locations and conditions that need to be satisfied to tap the true potential of the compensation scheme
Thus this work
Provides analytical model/solution for the architecture
Proposes a design procedure based on the analytical results
Design Example using the proposed design procedure
Simulation Results show the performance is orders of magnitude higher than miller compensation and far better than state of the art

22. Indirect Feedback Frequency Compensation
Improvements due to a simple change
The compensation current is indirectly fedback from low impedance node VA to V1
The RHP pole zero can be eliminated as the feedforward current is blocked by the common gate amplifier
Node V1 is now not loaded by the compensation capacitor (as previously) and thus results in a much faster second stage and increased unity gain frequency
AND MUCH MORE ………

23. Small Signal Analysis
TAKING KCL AT EACH
NODE

24. Simplified Transfer Function
The transfer function can be simplified and approximated as:-
The coefficients can be evaluated as
Evaluating the poles and zeros
Assuming the pole |p1| >> |p2|, |p3|
The denominator can now be
approximated
Real Poles
Complex Poles

25. bserving the Pole/Zero Locations
The third order transfer function as 3 poles and 1 zero
Dominant Pole location
Non-dominant Real Poles location
Condition For Real Poles
LHP Zero Location
Remains at the same location
Large gmc ?
Improves Phase Margin

26. Analytical Results Summary
Pole / Zero Location
Real Poles Condition
Extended by
a factor >1
Quick Facts
Pole p2 moved to much higher frequency
Can use much smaller gm5  Less Power
LHP zero improves the phase margin
Much faster op-amp with lower power and CC
Will EXPLORE more ….

27. Alternative Implementations of Indirect Feedback
The common gate amplifier is embedded in the cascode action
Similar to the common gate amplifier analyzed in the previous section, the LHP zero and the three poles are given by Equations provided previously
Reduction in Power at cost of Flexibility choosing the transconductance of gmc
Similar to cascoded PMOS loads
However additional RHP zero located at:
RHP zero
High Frequency

28. Summarizing the Advantages of Indirect Feedback
Pole splitting can be achieved with a much smaller compensation capacitor (Cc)
Faster Op Amp Much Smaller Area
Lower Value of second stage transconductance (gm5) value required
Lower Power and Less Total Current Required
Improved PSRR
Analytically the reason the non-dominant pole shifted to a higher frequency is because the compensation capacitor now does not load the first stage output.

29. Pre - Design Procedure Guidelines
Good Region
For AMI 0.5CN
VEB ≈ V
To quantify how good of a job our transistor does, we can therefore define the following “figure of merits (FOM)
Tranconductor Efficiency
Transit Frequency

30. Indirect Feedback Design Procedure Summary
Noise Specification
Gain-Bandwidth Requirement
Slew Rate Specification
Output Swing Specification
Real Poles Requirement

31. Class A Output Stage Design
Bad Output Stage Design
Not Controlling current in the output stage leads to:
Bad input-referred offset
Potential for large power dissipation
Not controlling output stage gm (and thus stability)
Class A output stages also suffer from poor slew rate

32. Class AB Output Stage Design
The Class AB output stage is realized by have a floating current source biased between the output stages transistors behaving like a push pull:
Slew Rate Improved during discharging
Controlled output stage current and gm
Slew rate limitation shifted to the compensation capacitor which is small in the proposed compensation scheme and thus achieves much higher slew rate

33. Figure of Merit (FOM)
To perform a comparison in terms of speed among the many compensation approaches independently of the particular amplifier topology, design choices, and technology, a figure of merit (FOM) that relates the load capacitance CL, the gain-bandwidth product ωGBW, and the total current consumption of the amplifier I­Total has been proposed [ref].
Small Signal FOM
DC Transient FOM
Single Stage Comparison
Total Transcoductance
Gm in multi-stage op amp

34. Design Example – Op Amp Specifications
Supply Voltages
± 1.25 V
Load Capacitance: CL
100 pF
Total Current (max)
30 μA
DC gain: Ao
70 dB
Unity-gain Frequency: fu
2 MHz
Phase Margin: φM
60°
Slew Rate: SR
1 V/μs
Input Common Mode Range: VCMR
± 1 V
Output Swing: Vout {max,min}
± 0.5 V
Input Referred Noise
15 nV/√Hz
Large Load
Very Low Power
Good Stability

35. Design Example – Device Sizing
Op Amp Sizing
Transistor
Multiplier
Size (μm)
M1,2 2
4.05/0.9
M3,4
3.6/2.4 M5 6
10.05/1.5 M6 12
15/1.05 M7
1.65/1.05
M9,b11 10
1.65/4.05
Mb1 1
Mb2
Mb3
Mb4
2.4/1.05
Mb5
12/1.05
Mb6
Mb7
3/1.2
Mb8
Mb9,10
1.95/0.6 Cc -
5 pF
Isupply
1.25uA

36. Summary of Simulated Results
Specification
Specifications
Simulation
DC gain: Ao
70 dB
72.45 dB
Unity-Gain Frequency: fu
2 MHz
2.01 MHz
Phase Margin: φM
60°
61.83°
Slew Rate: SR+/-
± 1 V/μs
1/-2.45 V/μs
Input Common Mode Range:
VCMR + / VCMR=
± 0.5 V
1.1/-0.75 V
Output Swing:
Vout MAX/Vout MIN
± 1 V
1.14/-1.1
ITotal
30 μA
Power -
75 μW
High Speed +
Low Power

37. AC Frequency Response (CL = 100pf)
Bandwidth Extension

38. Large Signal Transient Response (CL = 100pf)

39. Sine Wave Transient Response (CL = 100pf)

40. Robustness of Analytical Results
Small Error

41. Alternative Indirect Feedback Compensation Scheme Results
Comparison of Alternative Indirect Feedback Compensation
Specification
Common Gate
Cascode NMOS
Cascode PMOS
DC gain: Ao
72.45 dB
91.1 dB
86.1 dB
Unity-Gain Frequency: fu
2.01 MHz
1.99 MHz
2.2 MHz
Phase Margin: φM
61.83˚
61.29˚
61.7˚
Improved gain due
To cascoding
Common Gate
Cascode NMOS
Cascode PMOS

42. Comparison with Miller Compensation and Single Stage Amplifiers
Performance Comparison to Miller Compensation and Single Stage Amplifiers
Comparison with Miller Compensation and Single Stage Amplifiers
Specification
Single Stage
Single Miler Compensation
Indirect Feedback Compensation
DC gain: Ao
36.93 dB
70.45 dB
72.45
Unity-Gain Frequency: fu
1.098 MHz
293.1 KHz
2.01 MHz
Phase Margin: φM
90˚
60.29˚
61.7˚
Cc Required
-NA-
35 pF
5 pF
Winner
Miller Compensation
Indirect Feedback
Single Stage

43. Performance Comparison to Literature

44. Floor Planning Considerations Orientation of Transistors
Power Distribution
Routing Ease
Current Mirror Matching

45. Final Layout