1. Progress Report
Chester Liu
2013/12/27

2. Demonstration Schedule
First version
QCIF (176 x 144)
Only H264-intra encoder
Run JM to decode bit stream
Expect to be done by 12/20
Platform ready (but with minor problem)
Second version
Add WZ encoder
Expect to be done by 1/3

3. Demonstration Platform
Hardware
FPGA board (DE2-115)
Camera module (MT9V125)
Wi-Fi module (RS9110)
Software
UDP packet receiver (using C)
Append SPS & PPS to the bit stream of one frame and store them in a file
Invoke JM to decode, the decoded frame is then stored in another file
Real-time video player (using Qt)
Periodically read the decoded file and display the frame on screen

4. Demonstration Platform
Video viewer
Camera module
Wi-Fi module

5. DVC System Architecture
I’ll revisit this topic when it’s finalized

6. Current Progress Specification Limitation Problems To do
QCIF with YUV420, about 30 frames per second
Limitation
Need re-synthesis for different Wi-Fi setting (IP, password, etc.)
Problems
System hang after a period of operation debugging
Probably UDP connection problem
To do
Hardware
Add WZ encoder
Refine system design
Software
Combine packet receiver and video viewer to reduce communication overhead

7. Conference Experience Sharing
Use FPGA to play the board game Blokus, 25 teams in total
16 hardware design
9 high-level synthesis