1. AVR – ATmega103(ATMEL) Architecture & Summary
31, March
Digital Sig. in Chollian

2. Features RISC architecture High performance & Low-power
121 Instructions
Most Single Clock Cycle Execution
32*8 General-purpose Working reg. + Peripheral Control Register
Up to 6 MIPS Throughput at 6 MHz

3. Features Data and Nonvolatile Program Memory
128K Bytes of In-System Programmable FLASH Memory
Endurance : 1,000 Write/Erase Cycles
4K Byte Internal SRAM
4K Bytes of In-System Programmable EEPROM
Endurance : 100,000 Write/Erase Cycles
Programming Lock for Flash Program and EEPROM Data Security

4. Features Peripheral Features On-chip Analog Comparator
Programmable Watchdog Timer w/ On-chip oscillator
Programmable Serial UART
Master/Slave SPI Serial Interface
Real-time Counter(RTC) w/ separate Oscillator
Two 8-bit Timer/Counters w/ Separate Prescaler and PWM
Expanded 16-bit Timer/Counter System w/ Separate Prescaler, Compare, Capture Modes and Dual 8-, 9- or 10-bit PWM
Programmable Watchdog Timer w/ On-ship Oscillator
8-channel, 10-bit ADC

5. Features Special Microcontroller Mode Specifications
Low-power Idle, Power Save and Power-down Modes
Software Selectable Clock Frequency
External and Internal Interrupt Sources
Specifications
Low-power, High-speed CMOS Process Technology
Fully Static Operation

6. Features Power Consumption at 4MHz, 3V, 25℃ I/O and Packages
Active : 5.5 ㎃
Idle Mode : 1.6 ㎃
Power-down Mode : < 1㎂
I/O and Packages
32 Programmable I/O Lines, 8 Output Lines, 8 Input Lines
64-lead TQFP
Operating Voltages
2.7 ~ 3.6 V (ATmega103L)
4.0 ~ 5.5 V (ATmega103)
Speed Grades
0 ~ 4 MHz(ATmega103L)
0 ~ 6 MHz(ATmega103)

7. Pin Configuration

8. Block Diagram

9. Architecture

10. Architecture Harvard architecture
Separate memories and buses for program and data
The program memory is accessed w/ a single-level pipeline
The program memory is In-System Programmable Flash memory
Developed in the last 1930s by Howard Aiken, a physicist at Harvard University
The Harvard MARK I computer became operational in 1944

11. Architecture Von Neumann
Used a single memory space for instructions as well as data
Simplified the design of the computer
The architecture of the ENIAC(Electronic Numerical Integrator and Calculator) which built from 1943 to 1946 at the University of Pennsylvania is Von Neumann
The machine could access only the instruction or the data at any one time
Historically, this limitation has not been serious in general purpose computing.
Standard for development of computer systems over the last 50 years

12. General-purpose Register File

13. Memory Configuration A

14. Memory Configuration B

15. I/O Memory

16. I/O Memory

17. I/O Memory

18. Reset Sources
Power-on Reset
External Reset
Watchdog Reset

19. Timer/Counters Timer/Counter0 Prescaler
Real Time Clock(RTC) : kHz
PCK0 is by default connected CK
By setting the AS0 bit in ASSR, connected TOSC1

20. Timer/Counters
Clock source
CK, CK/8, CK/64, CK/256, CK/1024 and Ext.

21. Watchdog Timer
separated on-chip oscillator

22. Serial Peripheral Interface
Full-duplex, 3-wire synchronous data transfer
Master or slave operation
LSB first or MSB first data transfer
Four programmable bit rates
End-of-transmission interrupt flag
Write collision flag protection
Wake-up from idle mode(slave mode only)

23. Serial Peripheral Interface

24. UART UART - Universal Asynchronous Receiver and Transmitter
Baud rate generator that can generate a large number of baud rates(bps)
High baud rates at low XTAL freq.
8 or 9 bits data
Noise filtering
Overrun detection
Framing Error detection
False Start Bit detection
Three separate interrupts
TX Complete
TX Data Register Empty
RX Complete

25. UART Transmitter

26. UART Receiver

27. UBRR table

28. Analog Comparator

29. Analog-to-Digital Converter
10-bit resolution ±2 LSB absolute accuracy
0.5 LSB integral non-linearity ㎲ conversion time
Up to 14 kSPS(Sample per second) Sleep mode noise canceler
Interrupt on ADC conversion complete 8 multiplexed input channels