1. Ratioed Logic
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2. EE141
Ratioed Logic
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3. EE141
Ratioed Logic
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4. EE141
Active Loads
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5. Pseudo-NMOS VTC Smaller load Lower static power consumption lower VOL
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Pseudo-NMOS VTC
0.0
0.5
1.0
1.5
2.0
2.5
3.0 V in
[V] o u t
W/L p
= 4
= 2
= 1
= 0.25
= 0.5
Smaller load
Lower static power consumption
lower VOL
Higher tPLH
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6. EE141
Improved Loads
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7. Improved Loads (2) Differential Cascode Voltage Switch Logic (DCVSL) V
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Improved Loads (2) V V DD DD M1 M2
Out
Out A A
PDN1
PDN2 B B V V SS SS
Differential Cascode Voltage Switch Logic (DCVSL)
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8. EE141
DCVSL Example
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9. Pass-Transistor Logic
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10. Pass-Transistor Logic
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Pass-Transistor Logic
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11. EE141
Example: AND Gate
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12. NMOS-Only Logic In Out x EE141 [V] e g a t l o V Time [ns] 3.0 2.0 1.0
0.0
0.5 1
1.5 2
Time [ns]
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13. NMOS-only Switch V does not pull up to 2.5V, but 2.5V - V
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NMOS-only Switch
C =
2.5 V
C =
2.5 V M 2
A =
2.5 V
A =
2.5 V B M B n C M 1 L V
does not pull up to 2.5V, but 2.5V - V B TN
Threshold voltage loss causes
static power consumption
NMOS has higher threshold than PMOS (body effect)
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14. NMOS Only Logic: Level Restoring Transistor
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NMOS Only Logic: Level Restoring Transistor V DD V
Level Restorer DD M r B M 2 X A M n
Out M 1
• Advantage: Full Swing
• Restorer adds capacitance, takes away pull down current at X
• Ratio problem
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15. Complementary Pass Transistor Logic
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Complementary Pass Transistor Logic
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16. Solution 3: Transmission Gate
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Solution 3: Transmission Gate C C A B A B C C
C =
2.5 V
A =
2.5 V B C L C
= 0 V
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17. Resistance of Transmission Gate
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Resistance of Transmission Gate
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18. Pass-Transistor Based Multiplexer
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Pass-Transistor Based Multiplexer S S
VDD
GND
In1 S S
In2
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19. EE141
Transmission Gate XOR B B M2 A A F M1
M3/M4 B B
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20. Transmission Gate Full Adder
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Transmission Gate Full Adder
Similar delays for sum and carry
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