1. Day 14: October 8, 2010 Performance
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems
Day 14: October 8, 2010
Performance
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2. Previously Delay as RC-charging Transistor Gate Capacitance
Drive Current
As a function of geometry (W/L)
Gate
Topology
Delay
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3. Today Miller Effect Sizing Large Fanout Data Dependent Delay
Asymmetry of Inputs
Impact of P & N Mobility differences
Large Fanin
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4. Gate-Drain Capacitance
What is the voltage across Vin—V2
When Vin=Vdd
When Vin=Gnd
What is DV across Vin—V2 when Vin switches from Vdd to Gnd?
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5. Miller Effect For an inverting gate
Capacitance between input and output must swing 2 Vhigh
Or…acts as double-sized capacitor
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6. Transistor Sizing What happens to Ids as a function of W?
What happens to Cg as a function of W?
Conclude: faster transistors present more load on their inputs
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7. First Order Delay R0 = Resistance of minimum size NMOS device
C0 = gate capacitance of minimum size NMOS device
Rdrive = R0/W
Cg = WC0
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8. Inverter Sizing
What is the impact of the delay on the middle inverter if double size of all the transistors?
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9. How Size Equal Rise and Fall mn=500cm2/Vs, mp=200cm2/Vs Rdrive=R0/2
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10. Sample Gate Internal stages have delay External depend on load
Assume (guarantee) all inputs same load
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11. Large Fanout What is delay if must drive fanout=100?
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12. What Delay?
What is delay here?
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13. How Size How size transistors to minimize delay?
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14. Try again
What is the delay here?
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15. …and Again
Delay here?
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16. Lesson Don’t drive large fanout with a single stage
Must scale up over a number of stages
…but not too many
Exact number will be technology dependent
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17. Lecture ended here
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18. Gates
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19. Data Dependent Delay Resistance depends on input values
 delay depends on input data
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20. How Size Equalize rise/fall times Rdrive=R0/2
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21. How Size
For equal rise fall
Rdrive=R0/2
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22. Input Load Input capacitance in each case?
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23. Observe Ratio of Input Load Capacitance to Output Drive Strength
Differs with gate function
Some gates give more drive per capacitive load we pay
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24. Which Implementation is Faster?
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25. Take Away?
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26. Input (A)Symmetry
If one input is known to be later than other, does it matter where it goes?
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27. How Size Equalize rise/fall times Rdrive=R0/2
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28. Increasing Fanin
What happens to input capacitance as fanin (k) increases
Keeping output drive the same
E.g. Rdrive=R0/2
k-input nand gate has input capacitance:
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29. Fanin Gates slow down with fanin Less drive per input capacitance
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30. Which is fastest? nand32 nand4-inv-nand4-inv-nand2 (nand2-inv)4-nand2
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31. Lesson Large gates are slow / inefficient
High capacitive load / drive strength
Small gates can be inefficient
Need many stages
Staging over moderate size gates minimizes delay
Exact size will be technology dependent
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32. Admin Project 1 Out Fall Break on Monday Next Lecture Wednesday
2 week assignment
Optimizing Performance
Recommended milestones for next week
Fall Break on Monday
No class
Next Lecture Wednesday
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33. Ideas First order reason in R0C0 units
Gates have different efficiencies
Drive strength per unit input capacitance
Greater N mobility (than P)
favors nand over nor
Large fanin and fanout slow gates
Decompose into stages
…but not too much
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