1. COMS 361 Computer Organization
Title: Logic Design
Date: 11/09/2004
Lecture Number: 18

2. Announcements
Homework 8
Due Thursday, 11/11/04

3. Review Representing numbers in binary Boolean Algebra Boolean Logic
Finish overflow
Boolean Algebra
Boolean Logic

4. Outline
Logic design
Decoder
Multiplexor
PLA
Simple ALU

5. Decoder Basic logic building block n-bit input 2^n outputs
Different inputs select different outputs
Binary number input
One output asserted (true, 1, on) all others are off
Decoder L0 L1
out0
out1
out2
out3
out4
out5
out6
out7

6. Decoder

7. Decoder 1 2

8. Decoder 1 2 1 2

9. Decoder 1 2 1 2 1 2

10. Decoder 1 2 1 2 1 2 1 2 2

11. Multiplexor Really a selector
Choose one input and connect it to an output
Selection is based on a control signal b a c s
mux s b a c

12. Multiplexor Can have more than 2 input multiplexor
Need more selector signals as the number of inputs increases b a o s
mux c 2

13. Multiplexor
Note: sum-of-products b a o s
mux c 2 s0 a s1 b o c

14. Multiplexor Multiplexors select one channel from a set of channels
A channel may contain more than a single bit
32 bits b a o s
mux 32

15. PLA
Sum-of-product representation corresponds to a programmable logic array(PLA)
Set of inputs
Input compliments
Two logic blocks
Utilizes the structure of the sum-of-products representation
and gates
or gates
inputs
outputs
product terms

16. PLA And gates form the sets of products
Products consists of any input or complement
Or gates form the logical sum of any number of product terms
Direct implementation of a truth table
Each 1 in the output of the truth table requires a product term
Single row in the PLA
Each 1 in the output of the truth table corresponds to a row of OR gates

17. Arithmetic and Logic Unit (ALU)
Computers brains
Addition
Subtraction
Logical and
Logical or
32-bit words in MIPS
32-bit registers
32-bit ALU
All bits are mostly treated the same
Make a 1-bit ALU
Connect 32, 1-bit ALU’s together to make a 32-bit ALU
Bit Slicing
Bit Slicing
Bit Slicing
Bit Slicing
Bit Slicing
Bit Slicing
Bit Slicing

18. 1-bit ALU Many different implementations
Difficult to decide the “best” way to build something
Don't want too many inputs to a single gate
Don’t want to have to go through too many gates
For our purposes, ease of comprehension is important

19. 1-bit logical AND and logical OR
AND two bits (a, b)
OR two bits (a, b)
Select desired logical output
Operation is set to 0 to select the logical AND
Operation is set to 1 to select the logical OR 1 a b
result
operation

20. 1-Bit Adder (Half Adder)
Two one bit numbers are to be added
Simple truth table
Sum is the exclusive or of a and b
Cout is the logical AND of a and b a b
Cout
Sum 1

21. 1-Bit Adder (Half Adder)
Sum
Cout

22. Full Adder More interesting when we add two (or more) bit numbers
All bits except the least significant bit (LSB, rightmost) must add 3-bits not 2-bits
The carry bit of the previous stage is needed to compute the sum and carry of the next bit
Full adder includes the carry bit from the previous stage: 3-bit input to be added
sum
Cout

23. Full Adder Build a truth table for full adding a single bit
Carry out (Cout) is 1 if
Both a and b are 1 or
Either a or b is 1, not both and Carry In (Cin) is 1
Sum is 1 if
an odd number of the three inputs is on
XOR of the 3 inputs

24. Full Adder
half adder a b
Cin
Sum
Cout

25. 2-bit adder Combine the half adder and the full adder
Bit 0 does not have a carry in (for now)
half adder a0 b0 C0 s0
full adder a1 b1 s2 s1

26. n-bit adder
Adders for any number of bits can be constructed by cascading full adders
The carry bit from one stage is computed and enters the next stage
Carry bit ripples along
The sum of two numbers is not available until the carry bit ripples to the last stage
n-bit adder means there are 2n - 1 logic gates the carry bit must traverse
Increases the time for addition
Add hardware complexity to increase the speed

27. 32-bit ALU
ALU for a single bit
32-bit ALU
Use a full adder for bit 0

28. Subtraction Two’s complement representation Clever Subtraction
Negate one operand
Add
Negation in two’s complement
Invert the bits
Add 1
Clever

29. Subtraction Two’s complement representation Clever Subtraction
Negate one operand
Add
Negation in two’s complement
Invert the bits
Add 1
CarryIn a 1 into the first adder
a – b = a + b’ + 1
Clever
Control Signals 1

30. slt Hardware support for the set-on-less-than instruction
slt is an arithmetic instruction
Produces a 1 if rs < rt and 0 otherwise
Use subtraction: (a-b) < 0 implies a < b
Support test for equality (beq $t5, $t6, $t7)
Use subtraction: (a-b) = 0 implies a = b

31. slt
Most of the bits are set to 0