1. Data manipulation instructions
Data manipulation instructions correspond to ALU operations.
For example, here is a possible addition instruction, and its equivalent using our register transfer notation:
This is similar to a high-level programming statement like
R0 = R1 + R2
Here, all of the operands are registers.
ADD R0, R1, R2
operation
destination
sources
operands
R0  R1 + R2
Register transfer instruction:
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2. More data manipulation instructions
Here are some other kinds of data manipulation instructions.
NOT R0, R1 R0  R1’
ADD R3, R3, #1 R3  R3 + 1
SUB R1, R2, #5 R1  R2 - 5
Some instructions, like the NOT, have only one operand.
In addition to register operands, constant operands like 1 and 5 are also possible. Constants are denoted with a hash mark in front.
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3. Relation to the datapath
These instructions reflect the design of our datapath from last week.
There are at most two source operands in each instruction, since our ALU has just two inputs.
The two sources can be two registers, or one register and one constant.
More complex operations like
R0  R1 + R2 - 3
must be broken down into several lower-level instructions.
Instructions have just one destination operand, which must be a register.
D data
Write
D address
A address
B address
A data
B data
Register File WR DA AA BA A B
ALU F Z N C V FS
S D1 D0 Q
Constant MB
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4. What about RAM?
Recall that our ALU has direct access only to the register file.
RAM contents must be copied to the registers before they can be used as ALU operands.
Similarly, ALU results must go through the registers before they can be stored into memory.
We rely on data movement instructions to transfer data between the RAM and the register file.
D data
Write
D address
A address
B address
A data
B data
Register File WR DA AA BA
Q D1 D0 S
RAM
ADRS
DATA CS
OUT MW
+5V A B
ALU F Z N C V FS MD
S D1 D0 Q
Constant MB
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5. Loading a register from RAM
A load instruction copies data from a RAM address to one of the registers.
LD R1,(R3) R1  M[R3]
Remember in our datapath, the RAM address must come from one of the registers—in the example above, R3.
The parentheses help show which register operand holds the memory address.
D data WR
Write DA
D address
Register File AA
A address
B address BA
A data
B data
Constant MB
S D1 D0 Q
RAM
ADRS
DATA
OUT
+5V CS A B
ALU F Z N C V FS MW WR
Q D1 D0 S MD
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6. Storing a register to RAM
A store instruction copies data from a register to an address in RAM.
ST (R3),R1 M[R3]  R1
One register specifies the RAM address to write to—in the example above, R3.
The other operand specifies the actual data to be stored into RAM—R1 above.
D data
Write
D address
A address
B address
A data
B data
Register File WR DA AA BA
Constant MB
S D1 D0 Q
RAM
ADRS
DATA CS WR
OUT MW
+5V A B
ALU F Z N C V FS
Q D1 D0 S MD
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7. Loading a register with a constant
With our datapath, it’s also possible to load a constant into the register file:
LD R1, #0 R1  0
Our example ALU has a “transfer B” operation (FS=10000) which lets us pass a constant up to the register file.
This gives us an easy way to initialize registers.
D data WR
Write DA
D address
Register File AA
A address
B address BA
A data
B data
Constant MB
S D1 D0 Q
RAM
ADRS
DATA
OUT
+5V CS A B
ALU F Z N C V FS MW WR
Q D1 D0 S MD
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8. Storing a constant to RAM
And you can store a constant value directly to RAM too:
ST (R3), #0 M[R3]  0
This provides an easy way to initialize memory contents.
D data
Write
D address
A address
B address
A data
B data
Register File WR DA AA BA
Constant MB
S D1 D0 Q
RAM
ADRS
DATA CS WR
OUT MW
+5V A B
ALU F Z N C V FS
Q D1 D0 S MD
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9. The # and ( ) are important!
We’ve seen several statements containing the # or ( ) symbols. These are ways of specifying different addressing modes.
The addressing mode we use determines which data are actually used as operands:
The design of our datapath determines which addressing modes we can use.
The second example above wouldn’t work in our datapath. Why not?
We’ll talk about addressing modes in more detail next week.
LD R0, #1000 // R0  1000
LD R0, // R0  M[1000]
LD R3, R0 // R3  R0
LD R3, (R0) // R3  M[R0]
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10. A small example Here’s an example register-transfer operation.
M[1000]  M[1000] + 1
This is the assembly-language equivalent:
An awful lot of assembly instructions are needed!
For instance, we have to load the memory address 1000 into a register first, and then use that register to access the RAM.
This is due to our relatively simple datapath design, which only allows register and constant operands to the ALU.
Later on, mostly in CS232, you’ll see why this can be a good thing.
LD R0, #1000 // R0  1000
LD R3, (R0) // R3  M[1000]
ADD R3, R3, #1 // R3  R3 + 1
ST (R0), R3 // M[1000]  R3
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11. Control flow instructions
Programs consist of a lot of sequential instructions, which are meant to be executed one after another.
Thus, programs are stored in memory so that:
Each program instruction occupies one address.
Instructions are stored one after another.
A program counter (PC) keeps track of the current instruction address.
Ordinarily, the PC just increments after executing each instruction.
But sometimes we need to change this normal sequential behavior, with special control flow instructions.
768: LD R0, #1000 // R0  1000
769: LD R3, (R0) // R3  M[1000]
770: ADD R3, R3, #1 // R3  R3 + 1
771: ST (R0), R3 // M[1000]  R3
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12. Jumps A jump instruction always changes the value of the PC.
The operand specifies exactly how to change the PC.
For simplicity, we often use labels to denote actual addresses.
For example, a program can skip certain instructions.
You can also use jumps to repeat instructions.
LD R1, #10
LD R2, #3
JMP L
K LD R1, #20 // These two instructions
LD R2, #4 // would be skipped
L ADD R3, R3, R2
ST (R1), R3
LD R1, #0
F ADD R1, R1, #1
JMP F // An infinite loop!
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13. Branches
A branch instruction may change the PC, depending on whether a given condition is true.
LD R1, #10
LD R2, #3
BZ R4, L // Jump to L if R4 == 0
K LD R1, #20 // These instructions may be
LD R2, #4 // skipped, depending on R4
L ADD R3, R3, R2
ST (R1), R3
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14. Types of branches Branch conditions are often based on the ALU result.
This is what the ALU status bits V, C, N and Z are used for. With them we can implement various branch instructions like the ones below.
Other branch conditions (e.g., branch if greater, equal or less) can be derived from these, along with the right ALU operation.
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15. High-level control flow
These jumps and branches are much simpler than the control flow constructs provided by high-level languages.
Conditional statements execute only if some Boolean value is true.
Loops cause some statements to be executed many times
// Find the absolute value of *X
R1 = *X;
if (R1 < 0)
R1 = -R1; // This might not be executed
R3 = R1 + R1;
// Sum the integers from 1 to 5
R1 = 0;
for (R2 = 1; R2 <= 5; R2++)
R1 = R1 + R2; // This is executed five times
R3 = R1 + R1;
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16. Translating the C if-then statement
We can use branch instructions to translate high-level conditional statements into assembly code.
Sometimes it’s easier to invert the original condition. Here, we effectively changed the R1 < 0 test into R1 >= 0.
R1 = *X;
if (R1 < 0)
R1 = -R1;
R3 = R1 + R1;
LD R1, (X) // R1 = *X
BNN R1, L // Skip MUL if R1 is not negative
MUL R1, R1, #-1 // R1 = -R1
L ADD R3, R1, R1 // R3 = R1 + R1
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17. Translating the C for loop
Here is a translation of the for loop, using a hypothetical BGT branch.
R1 = 0;
for (R2 = 1; R2 <= 5; R2++)
R1 = R1 + R2;
R3 = R1 + R1;
LD R1, #0 // R1 = 0
LD R2, #1 // R2 = 1
FOR BGT R2, #5, L // Stop when R2 > 5
ADD R1, R1, R2 // R1 = R1 + R2
ADD R2, R2, #1 // R2++
JMP FOR // Go back to the loop test
L ADD R3, R1, R1 // R3 = R1 + R1
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18. ISA Summary
Machine language is the interface between software and processors.
High-level programs must be translated into machine language before they can be run.
There are three main categories of instructions.
Data manipulation operations, such as adding or shifting
Data transfer operations to copy data between registers and RAM
Control flow instructions to change the execution order
Instruction set architectures depend highly on the host CPU’s design.
The instructions that we saw today would be appropriate for our datapath from last week.
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19. Instruction encoding
We’ve already seen some important aspects of processor design.
A datapath contains an ALU, registers and memory.
Programmers and compilers use instruction sets to issue commands.
Now let’s complete our processor with a control unit that converts assembly language instructions into datapath signals.
Today we’ll see how control units fit into the big picture, and how assembly instructions can be represented in a binary format.
Next lecture, we’ll show all of the implementation details for our sample datapath and assembly language.
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20. Block diagram of a processor
The control unit connects programs with the datapath.
It converts program instructions into control words for the datapath, including signals WR, DA, AA, BA, MB, FS, MW, MD.
It executes program instructions in the correct sequence.
It generates the “constant” input for the datapath.
The datapath also sends information back to the control unit. For instance, the ALU status bits V, C, N, Z can be inspected by branch instructions to alter a program’s control flow.
Program
Control signals
Control
Unit
Datapath
Status signals
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21. A specific instruction set
The first thing we must do is agree upon an instruction set.
For our example CPU let’s stick with the three-address, register-to-register instruction set architecture introduced yesterday.
Data manipulation instructions have one destination and up to two sources, which must be either registers or constants.
We include dedicated load and store instructions to transfer data to and from memory.
Later, we’ll learn about different kinds of instruction sets.
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22. From assembly to machine language
Next, we must define a machine language, or a binary representation of the assembly instructions that our processor supports.
Our CPU includes three types of instructions, which have different operands and will need different representations.
Register format instructions require two source registers.
Immediate format instructions have one source register and one constant operand.
Jump and branch format instructions need one source register and one constant address.
Even though there are three different instruction formats, it is best to make their binary representations as similar as possible.
This will make the control unit hardware simpler.
We’ll start by making all of our instructions 16 bits long.
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23. Register format An example register-format instruction: ADD R1, R2, R3
An example register-format instruction:
ADD R1, R2, R3
Our binary representation for these instructions will include:
A 7-bit opcode field, specifying the operation (e.g., ADD).
A 3-bit destination register, DR.
Two 3-bit source registers, SA and SB.
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24. Immediate format An example immediate-format instruction:
An example immediate-format instruction:
ADD R1, R2, #3
Immediate-format instructions will consist of:
A 7-bit instruction opcode.
A 3-bit destination register, DR.
A 3-bit source register, SA.
A 3-bit constant operand, OP.
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25. PC-relative jumps and branches
We will use PC-relative addressing for jumps and branches, where the operand specifies the number of addresses to jump or branch from the current instruction.
We can assume each instruction occupies one word of memory.
The operand is a signed number.
It’s possible to jump or branch either “forwards” or “backwards.”
Backward jumps are often used to implement loops; see some of the examples from last week.
LD R1, # LD R1, #10
LD R2, # LD R2, #3
JMP L 1002 JMP 2
K LD R1, # LD R1, #20
LD R2, # LD R2, #4
L ADD R3, R3, R ADD R3, R3, R2
ST (R1), R ST (R1), R3
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26. Jump and branch format Two example jump and branch instructions:
Two example jump and branch instructions:
BZ R3, -24
JMP 18
Jump and branch format instructions include:
A 7-bit instruction opcode.
A 3-bit source register SA for branch conditions.
A 6-bit address field, AD, for storing jump or branch offsets.
Our branch instructions support only one source register. Other types of branches can be simulated from these basic ones.
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27. The address field AD
AD is treated as a six-bit signed number, so you can branch up to 31 addresses forward (25-1), or up to 32 addresses backward (-25).
The address field is split into two parts for uniformity, so the SA field occupies the same position in all three instruction formats.
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28. Instruction format uniformity
Notice the similarities between the different instruction formats.
The Opcode field always appears in the same position (bits 15-9).
DR is in the same place for register and immediate instructions.
The SA field also appears in the same position, even though this forced us to split AD into two parts for jumps and branches.
Tomorrow we’ll see how this leads to a simpler control unit.
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29. Instruction formats and the datapath
The instruction format and datapath are inter-related.
Since register addresses (DR, SA and SB) are three bits each, this instruction set can only support eight registers.
The constant operand (OP) is also three bits long. Its value will have to be sign-extended if the ALU supports wider inputs and outputs.
Conversely, supporting more registers or larger constants would require us to increase the length of our machine language instructions.
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30. Organizing our instructions
How can we select binary opcodes for each possible operation?
In general, “similar” instructions should have similar opcodes. Again, this will lead to simpler control unit hardware.
We can divide our instructions into eight different categories, each of which require similar datapath control signals.
To show the similarities within categories, we’ll look at register-based ALU operations and memory write operations in detail.
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31. Register format ALU operations
ADD R1, R2, R3
All register format ALU operations need the same values for the following control signals:
MB = 0, because all operands come from the register file.
MD = 0 and WR = 1, to save the ALU result back into a register.
MW = 0 since RAM is not modified. WR 1 D
Register file
A B DA AA BA
A B
ALU G FS V C N Z
Mux B MB
Mux D MD
ADRS DATA
Data RAM
OUT MW
constant
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32. Memory write operations
ST (R0), R1
All memory write operations need the same values for the following control signals:
MB = 0, because the data to write comes from the register file.
MD = X and WR = 0, since none of the registers are changed.
MW = 1, to update RAM. WR D
Register file
A B DA AA BA
A B
ALU G FS V C N Z
Mux B MB
Mux D MD X
ADRS DATA
Data RAM
OUT MW 1
constant
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33. Selecting opcodes
Instructions in each of these categories are similar, so it would be convenient if those instructions had similar opcodes.
We’ll assign opcodes so that all instructions in the same category will have the same first three opcode bits (bits of the instruction).
Next time we’ll talk about the other instruction categories shown here.
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34. ALU and shift instructions
What about the rest of the opcode bits?
For ALU and shift operations, let’s fill in bits 12-9 of the opcode with FS3-FS0 of the five-bit ALU function select code.
For example, a register-based XOR instruction would have the opcode
The first three bits 000 indicate a register-based ALU instruction.
1100 denotes the ALU XOR function.
An immediate shift left instruction would have the opcode
101 indicates an immediate shift.
1000 denotes a shift left.
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35. Branch instructions
We’ll implement branch instructions for the eight different conditions shown here.
Bits 11-9 of the opcode field will indicate the type of branch. (We only need three bits to select one of eight branches, so opcode bit 12 won’t be needed.)
For example, the branch if zero instruction BZ would have the opcode 110x011.
The first three bits 110 indicate a branch.
011 specifies branch if zero.
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36. Sample opcodes
Here are some more examples of instructions and their corresponding opcodes in our instruction set.
Several opcodes have unused bits.
We only need three bits to distinguish eight types of branches.
There is only one kind of jump and one kind of load instruction.
These unused opcodes allow for future expansion of the instruction set. For instance, we might add new instructions or new addressing modes.
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37. Sample instructions
Here are complete translations of the instructions.
The meaning of bits 8-0 depends on the instruction format.
The colors are not supposed to blind you, but to help you distinguish between destination, source, constant and address fields.
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38. Summary
Today we defined a binary machine language for the instruction set from yesterday.
Different instructions have different operands and formats, but keeping the formats uniform will help simplify our hardware.
We also try to assign similar opcodes to “similar” instructions.
The instruction encodings and datapath are closely related. For example, our opcodes include ALU selection codes, and the number of available registers is limited by the size of each instruction.
This is just one example of how to define a machine language. You will be using a different instruction encoding for MP4, for instance.
Next, we’ll show how to build a control unit corresponding to our datapath and instruction set. This will complete our processor!
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