1. Welcome to Architectures of Digital Systems
Prof. Giancarlo Succi, Ph.D., P.Eng.
Prof. G. Succi, Ph.D., P.Eng.

2. Computer Systems Architecture
A lively class
I speak fast and I do not like people who do not pose questions and interrupt me … 
Let’s have a look at the web…
Prof. G. Succi, Ph.D., P.Eng.

3. What This course is not Learning C C Assembly Language Programming C++
If you know one, you should be able to learn another programming language largely on your own
Given that you know Java, should be easy to pick up their ancestor, C
Assembly Language Programming
This is a skill you will pick up, as a side effect of understanding the Big Ideas
Hardware design
We think of hardware at the abstract level, with only a little bit of physical logic to give things perspective C
C++
Java
Prof. G. Succi, Ph.D., P.Eng.

4. Structure of a Computer System
Prof. G. Succi, Ph.D., P.Eng.

5. Plan of the lecture
We will discuss the overall structure of a computer system, with specific attention to its main constituents
Prof. G. Succi, Ph.D., P.Eng.

6. Topics The idea of automatic execution Overall structure ALU CU
Registers
Prof. G. Succi, Ph.D., P.Eng.

7. From http://sc.essortment.com/saucespestopas_odu.htm
Automatic execution
From
Prof. G. Succi, Ph.D., P.Eng.

8. How do we direct the execution of the recipe?
What do we need?
How do we proceed?
Where do we store the recipe?
An executor capable of doing these things
A sequencer that remembers where we are
Some place to put what we have processed so far
A pot where to place the final result
Prof. G. Succi, Ph.D., P.Eng.

9. (or Central Processing Unit –CPU).
The stored program
Fetch the instruction
Decode the instruction
Execute the instruction
DISK
bus
Inside the Processor
(or Central Processing Unit –CPU).
Prof. G. Succi, Ph.D., P.Eng.

10. HW and SW software instruction set hardware
Prof. G. Succi, Ph.D., P.Eng.

11. ALU CU Structure of the CPU BUS Main Memory register register
Prof. G. Succi, Ph.D., P.Eng.

12. The CU Is the core of the sequencing of operations
Picks the new operation to be executed
Decodes it
Coordinates its execution
Prof. G. Succi, Ph.D., P.Eng.

13. The ALU Is the core of the “computation”
Performs arithmetic, logic and shift operations
All other operations are combinations of these basic operations
Works on numbers in base 2, usually (more next lecture)
Prof. G. Succi, Ph.D., P.Eng.

14. The registers
Are the places where we put the data we need for the actual execution
Limited in size and very fast to access
Prof. G. Succi, Ph.D., P.Eng.

15. The bus The interconnection between the different pieces
There are different kinds, supporting different speed and sizes
Prof. G. Succi, Ph.D., P.Eng.

16. Main memory Addressed directly –sometimes said “randomly,” hence RAM
Fast access, no as fast as register, but still fast
Volatile structure
Prof. G. Succi, Ph.D., P.Eng.

17. Disk storage Slower to access Sequential in accessing nature
Larger capacity
Permanent storage
Prof. G. Succi, Ph.D., P.Eng.

18. Anatomy: 5 components of any Computer
Processor
Computer
Control
(“brain”)
Datapath
(“brawn”)
Memory
(where
programs,
data
live when
running)
Devices
Input
Output
Keyboard, Mouse
Display, Printer
Disk (where
not running)
That is, any computer, no matter how primitive or advance, can be divided into five parts:
1. The input devices bring the data from the outside world into the computer.
2. These data are kept in the computer’s memory until ...
3. The datapath request and process them.
4. The operation of the datapath is controlled by the computer’s controller.
All the work done by the computer will NOT do us any good unless we can get the data back to the outside world.
5. Getting the data back to the outside world is the job of the output devices.
The most COMMON way to connect these 5 components together is to use a network of busses.
Prof. G. Succi, Ph.D., P.Eng.

19. Input devices
Prof. G. Succi, Ph.D., P.Eng.

20. Output devices
Prof. G. Succi, Ph.D., P.Eng.

21. Computer Technology Dramatic Change!
Processor
2X in speed every 1.5 years (since ‘85); 100X performance in last decade.
Memory
DRAM capacity: 2x / 2 years (since ‘96); 64x size in last decade.
Disk
Capacity: 2X / 1 year (since ‘97)
250X size in last decade.
Prof. G. Succi, Ph.D., P.Eng.

22. Evolution: Memory Capacity Single-Chip DRAM)
year size (Mbit)
/16 /4
1986 1
1989 4
Discuss what is the MBit
Now 1.4X/yr, or 2X every 2 years.
4000X since 1980.
Prof. G. Succi, Ph.D., P.Eng.

23. Computer Technology Dramatic Change!
State-of-the-art PC when you graduate:
Processor clock speed: 10,000 MHz (10.0 GHz)
Memory capacity: 10,000 MB (10.0 GB)
Disk capacity: 20,000 GB (20.0 TB)
New units! Mega => Giga, Giga => Tera
Prof. G. Succi, Ph.D., P.Eng.

24. Evolution: Microprocessor Complexity
Athlon (K7): 22 Million
Alpha 21264: 15 million
Pentium Pro: 5.5 million
PowerPC 620: 6.9 million
Alpha 21164: 9.3 million
Sparc Ultra: 5.2 million
Moore’s Law
2X transistors/Chip
Every 1.5 years
Called
“Moore’s Law”
Prof. G. Succi, Ph.D., P.Eng.

25. Evolution: Processor Performance
Intel P MHz
(Fall 2001)
1.54X/yr
Processor performance increase/year, inaccurately
referred to as Moore’s Law (really transistors/chip)
Prof. G. Succi, Ph.D., P.Eng.

26. Life can be more complex
TI SuperSPARCtm TMS390Z50 - Sun SPARCstat20
MBus Module
SuperSPARC
Floating-point Unit L2 $ CC
DRAM
Controller
Integer Unit
MBus
L64852
MBus control
M-S Adapter
Inst
Cache
Ref
MMU
Data
Cache
STDIO
SBus
serial
Store
Buffer
SCSI
kbd
SBus
DMA
mouse
Ethernet
audio
RTC
Bus Interface
SBus
Cards
Boot PROM
Floppy
Prof. G. Succi, Ph.D., P.Eng.